Versatile Data Acquisition and Controls for Epics Using Vme-Based Fpgas

Field-Programmable Gate Arrays (FPGAs) have provided Thomas Jefferson National Accelerator Facility (Jefferson Lab) with versatile VME-based data acquisition and control interfaces with minimal development times. FPGA designs have been used to interface to VME and provide control logic for numerous systems. The building blocks of these logic designs can be tailored to the individual needs of each system and provide system operators with read-backs and controls via a VME interface to an EPICS based computer. This versatility allows the system developer to choose components and define operating parameters and options that are not readily available commercially. Jefferson Lab has begun developing standard FPGA libraries that result in quick turn around times and inexpensive designs.Comment: 3 pages, ICALEPCS 2001, T. Allison and R. Foold, Jefferson La

Proceedings of the NSSDC Conference on Mass Storage Systems and Technologies for Space and Earth Science Applications

The proceedings of the National Space Science Data Center Conference on Mass Storage Systems and Technologies for Space and Earth Science Applications held July 23 through 25, 1991 at the NASA/Goddard Space Flight Center are presented. The program includes a keynote address, invited technical papers, and selected technical presentations to provide a broad forum for the discussion of a number of important issues in the field of mass storage systems. Topics include magnetic disk and tape technologies, optical disk and tape, software storage and file management systems, and experiences with the use of a large, distributed storage system. The technical presentations describe integrated mass storage systems that are expected to be available commercially. Also included is a series of presentations from Federal Government organizations and research institutions covering their mass storage requirements for the 1990's

The CMS Drift Tube Trigger Track Finder

Muons are among the decay products of many new particles that may be discovered at the CERN Large Hadron Collider. At the first trigger level the identification of muons and the determination of their transverse momenta and location is performed by the Drift Tube Trigger Track Finder in the central region of the Compact Muon Solenoid experiment, using track segments detected in the Drift Tube muon chambers. Track finding is performed both in pseudorapidity and azimuth. Track candidates are ranked and sorted, and the best four are delivered to the subsequent high level trigger stage. The concept, design, control and simulation software as well as the expected performance of the system are described. Prototyping, production and tests are also summarized

Implementation of a real-time industrial web scanning system hardware architecture

None provided

A Multiprocessor three-dimensional graphics systems.

by Hui Chau Man.Thesis (M.Phil.)--Chinese University of Hong Kong, 1991.Includes bibliographical references.ABSTRACT --- p.iACKNOWLEDGEMENTS --- p.iiTABLE OF CONTENTS --- p.iiiChapter CHAPTER 1 --- INTRODUCTIONChapter 1.1 --- Computer Graphics Today --- p.2Chapter 1.1.1 --- 3D Graphics Synthesis Techniques --- p.2Chapter 1.1.2 --- Hardware-assisted Computer Graphics --- p.4Chapter 1.2 --- About The Thesis --- p.5Chapter CHAPTER 2 --- GRAPHICS SYSTEM ARCHITECTURESChapter 2.1 --- Basic Structure of a Graphics Subsystem --- p.8Chapter 2.2 --- VLSI Graphics Chips --- p.9Chapter 2.2.1 --- The CRT Controllers --- p.10Chapter 2.2.2 --- The VLSI Graphics Processors --- p.11Chapter 2.2.3 --- Design Philosophies for VLSI Graphics Processors --- p.12Chapter 2.3 --- Graphics Boards --- p.14Chapter 2.3.1 --- The ARTIST 10 Graphics Controller --- p.14Chapter 2.3.2 --- The MATROX PG-1281 Graphics Controller --- p.16Chapter 2.4 --- High-end Graphics System Architectures --- p.17Chapter 2.4.1 --- Graphics Accelerator with Multiple Functional Units --- p.18Chapter 2.4.2 --- Parallel Processing Graphics Systems --- p.18Chapter 2.4.3 --- The Parallel Processor Architecture --- p.19Chapter 2.4.4 --- The Pipelined Architecture --- p.21Chapter 2.5 --- Comparisons and Discussions --- p.22Chapter 2.5.1 --- Parallel Processors versus Pipelined Processing --- p.23Chapter 2.5.2 --- Parallel Processors versus Multiple Functional Units --- p.23Chapter 2.6 --- Summary of High-end Graphics Systems --- p.24Chapter CHAPTER 3 --- AN ISA 3D GRAPHICS DISPLAY SERVERChapter 3.1 --- Common ISA Graphics Cards --- p.26Chapter 3.1.1 --- Standard Video Display Cards --- p.26Chapter 3.1.2 --- Graphics Processing Boards --- p.27Chapter 3.2 --- A Depth Processor for the ISA computers --- p.28Chapter 3.2.1 --- The Z-buffer Algorithm for HLHSR --- p.28Chapter 3.2.2 --- Our Hardware Solution for HLHSR --- p.29Chapter 3.2.3 --- Design of the Depth Processor --- p.31Chapter 3.2.4 --- Structure of the Depth Processor --- p.34Chapter 3.2.5 --- The Depth Processor Operations --- p.35Chapter 3.2.6 --- Software Support --- p.40Chapter 3.2.7 --- Performance of the Depth Processor --- p.44Chapter 3.3 --- A VGA Accelerator for the ISA Computers --- p.45Chapter 3.3.1 --- Display Buffer Structure of the SuperVGA --- p.46Chapter 3.3.2 --- Design of the VGA Accelerator --- p.47Chapter 3.3.3 --- Structure of the VGA Accelerator --- p.49Chapter 3.3.4 --- Combining the VGA Accelerator and the Depth Processor --- p.51Chapter 3.3.5 --- Actual Performance of the DP-VA Board --- p.54Chapter 3.3.6 --- 3D Graphics Applications Using the DP-VA Board --- p.55Chapter 3.4 --- A 3D Graphics Display Server --- p.57Chapter 3.5 --- Host Connection for the 3D Graphics Display Server --- p.59Chapter 3.5.1 --- The Single Board Computers --- p.60Chapter 3.5.2 --- The VME-to-ISA bus convenor --- p.61Chapter 3.5.3 --- Structure of the VME-to-ISA Bus Convertor --- p.61Chapter 3.5.4 --- Communications through the bus convertor --- p.64Chapter 3.6 --- Physical Construction of the DP-VA Board and the Bus Convertor --- p.65Chapter 3.7 --- Summary --- p.66Chapter CHAPTER 4 --- A MULTI-i860 3D GRAPHICS SYSTEMChapter 4.1 --- The i860 Processor --- p.69Chapter 4.2 --- Design of a Multiprocessor 3D Graphics System --- p.70Chapter 4.2.1 --- A Reconfigurable Processor-Pipeline System --- p.72Chapter 4.2.2 --- The Depth-Processing Unit --- p.73Chapter 4.2.3 --- A Multiprocessor Graphics System --- p.75Chapter 4.3 --- Structure of the Multi-i860 3D --- p.77Chapter 4.3.1 --- The 64-bit-wide Global Data Buses --- p.77Chapter 4.3.2 --- The 1280x1024 True-colour Display Unit --- p.79Chapter 4.3.3 --- The Depth Processing Unit --- p.82Chapter 4.3.4 --- The i860 Processing Units --- p.84Chapter 4.3.5 --- The System Control Unit --- p.87Chapter 4.3.6 --- Performance Prediction --- p.89Chapter 4.4 --- Summary --- p.90Chapter CHAPTER 5 --- CONCLUSIONSChapter 5.1 --- The 3D Graphics Synthesis Pipeline ……… --- p.91Chapter 5.2 --- 3D Graphics Hardware --- p.91Chapter 5.3 --- Design Approach for the ISA 3D Graphics Display Server --- p.92Chapter 5.4 --- Flexibility in the Multi-i860 3D Graphics System --- p.93Chapter 5.5 --- Future Work --- p.94Chapter APPENDIX A --- DISPLAYING REALISTIC 3D SCENESChapter A.1 --- Modelling 3D Objects in Boundary Representation --- p.96Chapter A.2 --- Transformations of 3D scenes --- p.98Chapter A.2.1 --- Composite Modelling Transformation --- p.98Chapter A.2.2 --- Viewing Transformations --- p.99Chapter A.2.3 --- Projection --- p.102Chapter A.2.4 --- Window to Viewport Mapping --- p.104Chapter A.3 --- Implementation of the Viewing Pipeline --- p.105Chapter A.3.1 --- Defining the View Volume --- p.105Chapter A.3.2 --- Normalization of The View Volume --- p.106Chapter A.3.3 --- The Overall Transformation Pipeline --- p.108Chapter A.4 --- Rendering Realistic 3D Scenes --- p.108Chapter A.4.1 --- Scan-conversion of Lines and Polygons --- p.108Chapter A.4.2 --- Hidden Surface Removal --- p.109Chapter A.4.3 --- Shading --- p.112Chapter A.4.4 --- The Complete 3D Graphics Pipeline --- p.114Chapter APPENDIX B --- DEPTH PROCESSOR DESIGN DETAILSChapter B.l --- PAL Definitions --- p.116Chapter B.2 --- Circuit Diagrams --- p.118Chapter B.3 --- Depth Processor User's Guide --- p.121Chapter APPENDIX C --- VGA ACCELERATOR DESIGN DETAILSChapter C.1 --- PAL Definitions --- p.124Chapter C.2 --- Circuit Diagram --- p.125Chapter C.3 --- The DP-VA User's Guide --- p.127Chapter APPENDIX D --- VME-TO-ISA BUS CONVERTOR DESIGN DETAILSChapter D.1 --- PAL Definitions --- p.131Chapter D.2 --- Circuit Diagrams --- p.133Chapter APPENDIX E --- 3D GRAPHICS LIBRARY ROUTINES FOR THE DP-VA BOARDChapter E.1 --- 3D Drawing Routines --- p.136Chapter E.2 --- 3D Transformation Routines --- p.137Chapter E.3 --- Shading Routines --- p.138Chapter APPENDIX F --- PIPELINE CONFIGURATIONS FOR N PROCESSORSREFERENCE

A PCI Express board designed to interface with the electronic phase-2 upgrades of the ATLAS detectors at CERN

Nei prossimi 10 anni è in previsione un aggiornamento radicale dell'acceleratore LHC al CERN finalizzato al raggiungimento di più alti valori di luminosità istantanea (oltre \begin{math}5 \times 10^{34}cm^{-2}s^{-1}\end{math}) ed integrata (oltre un fattore 10 rispetto a quella attuale). Conseguentemente, anche i rilevatori degli esperimenti che lavorano al CERN, così come i loro sistemi di acquisizione dati, dovranno essere aggiornati per poter gestire un flusso notevolmente maggiore rispetto a quello utilizzato finora. Questa tesi tratta in particolare di una nuova scheda elettronica di lettura, progettata e testata nel laboratorio di elettronica del Dipartimento di Fisica ed Astronomia dell'Università di Bologna e nel laboratorio di elettronica della Sezione INFN (Istituto Nazionale di Fisica Nucleare) di Bologna. Le motivazioni che hanno indotto lo sviluppo della scheda prototipale sono molteplici. Un primo obiettivo da perseguire è stato quello di aggiornare la versione attuale delle schede elettroniche di acquisizione dati usate oggi nel Pixel Detector dell'esperimento ATLAS, visto che sono anch'esse sotto la responsabilità della sezione INFN di Bologna. Secondariamente, la scheda (nominata Pixel-ROD) è orientata a gestire le esigenze elettroniche che seguiranno l'upgrade di LHC durante la fase 2. La complessità del progetto e l'inerzia intrinseca di una vasta collaborazione come quella di ATLAS, hanno poi indotto lo sviluppo di questo progetto elettronico in largo anticipo rispetto al vero upgrade di fase 2 di LHC, previsto per il 2024. In questo modo saranno anche più facilmente eseguibili eventuali aggiornamenti tecnologici in corso d'opera, senza dover riprogettare da zero un sistema di acquisizione dati completo

The architecture of a video image processor for the space station

The architecture of a video image processor for space station applications is described. The architecture was derived from a study of the requirements of algorithms that are necessary to produce the desired functionality of many of these applications. Architectural options were selected based on a simulation of the execution of these algorithms on various architectural organizations. A great deal of emphasis was placed on the ability of the system to evolve and grow over the lifetime of the space station. The result is a hierarchical parallel architecture that is characterized by high level language programmability, modularity, extensibility and can meet the required performance goals