CMOS ring oscillator delay cell performance: a comparative study

A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell

Design of a Time Based Analog to Digital Converter

Analog to digital converter (ADC) plays a very important role in any mixed analog/digital system. Because digital CMOS technology can take advantage of technology scaling, system designers try to increase the percentage of the digital part of the system. This means moving the ADC more and more towards the input of the system which results in making the role of the ADC more and more critical. With technology scaling, the switching characteristics of MOS transistors offer superb timing accuracy at high frequencies. This makes the time based analog to digital converter (TADC) a good alternative to the conventional ADCs in sub-micron region. In this thesis, an all digital TADC structure is proposed. This TADC is based on an analog to time converter (ATC), followed by a time to digital converter (TDC). The TDC is based on sigma-delta modulation. A non-linear multi-bit internal quantizer in sigma-delta modulator is used to counteract the nonlinearity introduced when the VCO is used as the ATC. The novel TADC also uses an implicit sample and hold (S/H) circuit to reduce area. Dynamic element matching (DEM) is used to improve the robustness of the system against random mismatch in the multi-bit quantizer. Both first and second order sigma-delta modulator TADC are proposed. Simulations and measurements on the proposed TADC are provided. Measurements, from a prototype chip fabricated using 0.13um CMOS technology, show that the first order TADC has achieved a dynamic range of 11 bits for a bandwidth of 2MHz. While simulation results show a dynamic range of 12 bit. Simulations show that the second order TADC has achieved a dynamic range of 12bit for a bandwidth of 20MHz

ENABLING HARDWARE TECHNOLOGIES FOR AUTONOMY IN TINY ROBOTS: CONTROL, INTEGRATION, ACTUATION

The last two decades have seen many exciting examples of tiny robots from a few cm3 to less than one cm3. Although individually limited, a large group of these robots has the potential to work cooperatively and accomplish complex tasks. Two examples from nature that exhibit this type of cooperation are ant and bee colonies. They have the potential to assist in applications like search and rescue, military scouting, infrastructure and equipment monitoring, nano-manufacture, and possibly medicine. Most of these applications require the high level of autonomy that has been demonstrated by large robotic platforms, such as the iRobot and Honda ASIMO. However, when robot size shrinks down, current approaches to achieve the necessary functions are no longer valid. This work focused on challenges associated with the electronics and fabrication. We addressed three major technical hurdles inherent to current approaches: 1) difficulty of compact integration; 2) need for real-time and power-efficient computations; 3) unavailability of commercial tiny actuators and motion mechanisms. The aim of this work was to provide enabling hardware technologies to achieve autonomy in tiny robots. We proposed a decentralized application-specific integrated circuit (ASIC) where each component is responsible for its own operation and autonomy to the greatest extent possible. The ASIC consists of electronics modules for the fundamental functions required to fulfill the desired autonomy: actuation, control, power supply, and sensing. The actuators and mechanisms could potentially be post-fabricated on the ASIC directly. This design makes for a modular architecture. The following components were shown to work in physical implementations or simulations: 1) a tunable motion controller for ultralow frequency actuation; 2) a nonvolatile memory and programming circuit to achieve automatic and one-time programming; 3) a high-voltage circuit with the highest reported breakdown voltage in standard 0.5 μm CMOS; 4) thermal actuators fabricated using CMOS compatible process; 5) a low-power mixed-signal computational architecture for robotic dynamics simulator; 6) a frequency-boost technique to achieve low jitter in ring oscillators. These contributions will be generally enabling for other systems with strict size and power constraints such as wireless sensor nodes