A CMOS fully-differential bandpass ΣΔ modulator using switched-current circuits

This paper presents a fourth-order bandpass sigma-delta modulator that has been designed using fully-differential switched-current circuits in a 0.8μm CMOS technology. The modulator prototype has been obtained by applying a lowpass to bandpass transformation to a second-order lowpass ΣΔ modulator. Specifications are SNR [email protected]±15Khz, for a clock frequency of 1OMhz. Preliminary results from the fabricated prototype obtains the correct noise shaping up to 2.5Mhz clock frequency

A CMOS fully-differential bandpass ΣΔ modulator using switched-current circuits

Comunicación presentada al "38 th MWSCAS" celebrado en Rio de janeiro del 13 al 16 de Agosto de 1995.This paper presents a fourth-order bandpass sigma-delta modulator that has been designed using fully-differential switched-current circuits in a 0.8μm CMOS technology. The modulator prototype has been obtained by applying a lowpass to bandpass transformation to a second-order lowpass ΣΔ modulator. Specifications are SNR [email protected]±15Khz, for a clock frequency of 1OMhz. Preliminary results from the fabricated prototype obtains the correct noise shaping up to 2.5Mhz clock frequency.Peer reviewe

A CMOS 0.8- µm transistor-only 1.63-MHz switched-current bandpass ΣΔ modulator for AM signal A/D conversion

This paper presents a CMOS 0.8-/spl mu/m switched-current (SI) fourth-order bandpass /spl Sigma//spl Delta/ modulator (BP-/spl Sigma//spl Delta/M) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and 60-mW power consumption from a 5-V supply voltage. This modulator Is intended for direct A/D conversion of narrow-band signals within the commercial AM band, from 530 kHz to 1.6 MHz. Its architecture is obtained by applying a low-pass-to-bandpass transformation (z/sup -1//spl rarr/-z/sup -2/) to a 1-bit second-order low-pass /spl Sigma//spl Delta/ modulator (LP-/spl Sigma//spl Delta/M). The design of basic building blocks is based upon a detailed analysis of the influence of SI errors on the modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz.This work has been supported by the Spanish CICYT Project TIC 97-0580

Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications

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Experimental Characterization of IdleTones in Second-Order Bandpass ΣΔ Modulators

This paper analyses the tonal behaviour of the quantization noise in second-order bandpass ΣΔ modulators. The analysis performed for lowpass modulators is extended to the bandpass case. As a result, closed form expressions for the frequency of idle tones are derived for different cases regarding the signal center frequency position. All these results have been validated by measurements from a silicon prototype using fully differential switched-current circuits implemented in a standard 0.8μm CMOS technology.This work has been supported by the Spanish CICYT Project TIC 97-0580.Peer reviewe

Experimental Characterization of IdleTones in Second-Order Bandpass ΣΔ Modulators

This paper analyses the tonal behaviour of the quantization noise in second-order bandpass ΣΔ modulators. The analysis performed for lowpass modulators is extended to the bandpass case. As a result, closed form expressions for the frequency of idle tones are derived for different cases regarding the signal center frequency position. All these results have been validated by measurements from a silicon prototype using fully differential switched-current circuits implemented in a standard 0.8μm CMOS technology.Ministerio de Ciencia e Innovación CICYT TIC 97-058