A survey of FPGA-based LDPC decoders

Low-Density Parity Check (LDPC) error correction decoders have become popular in communications systems, as a benefit of their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into LDPC decoder designs that exploit the flexibility, the high processing speed and the parallelism of Field-Programmable Gate Array (FPGA) devices. FPGAs are ideal for design prototyping and for the manufacturing of small-production-run devices, where their in-system programmability makes them far more cost-effective than Application-Specific Integrated Circuits (ASICs). However, the FPGA-based LDPC decoder designs published in the open literature vary greatly in terms of design choices and performance criteria, making them a challenge to compare. This paper explores the key factors involved in FPGA-based LDPC decoder design and presents an extensive review of the current literature. In-depth comparisons are drawn amongst 140 published designs (both academic and industrial) and the associated performance trade-offs are characterised, discussed and illustrated. Seven key performance characteristics are described, namely their processing throughput, latency, hardware resource requirements, error correction capability, processing energy efficiency, bandwidth efficiency and flexibility. We offer recommendations that will facilitate fairer comparisons of future designs, as well as opportunities for improving the design of FPGA-based LDPC decoder

Fifth Generation (5G) New Radio (NR) Channel Codes Contenders Based on Field- Programmable Gate Arrays (FPGA): A Review Paper

ان الحاجة المتزايدة على الجودة، مثل السرعة العالية والتاخير المنخفض والتغطية الواسعة واستهلاك الطاقة والتكلفة والاتصالات الموثوقة في خدمات الهاتف المحمول والوسائط المتعددة ونقل البيانات تفرض استخدام المتطلبات التقنية المتقدمة في الجيل الخامس (5G) الإذاعة الجديدة (NR). واحدة من أهم الأجزاء في الطبقة المادية للجيل الجديد هي تقنية الترميز لتصحيح الأخطاء. هنالك ثلاثة اشكال مقترحة لتقنيات الترميز المخصصة لقنوات نقل البيانات وقنوات التحكم هي  الترميز التوربيني وفحص التكافؤ المنخفض الكثافة (LDPC) والرموز القطبية. يتم تقييم المنافسة بين هذه الانواع من حيث القدرة على تصحيح الأخطاء والتعقيد الحسابي والمرونة. التوازي والمرونة وسرعة المعالجة العالية لمصفوفة البوابة القابلة للبرمجة الميدانية (FPGA) تجعلها أفضل في النماذج الأولية وتنفيذ الرموز المختلفة. تقدم هذه الورقة دراسة استقصائية للبحوث الحالية التي تتعامل مع تصميم وحدة فك الترميز المستندة إلى FPGA المرتبطة برموز القناة المذكورة سابقًا.The increased demands for quality, like high throughput, low-latency, wide coverage, energy consumption, cost and reliable connections in mobile services, multimedia and data transmission impose the use of advance technical requirements for the next fifth-generation (5G) new radio (NR). One of the most crucial parts in the physical layer of the new generation is the error correction coding technique. Three schemes, namely; Turbo, low density parity check (LDPC), and polar codes are potentially ‎considered as the candidate codes for both data and control channels. The competition is evaluated in terms of error correction capability, computational complexity, and flexibility. The parallelism, flexibility and high processing speed of Field-Programmable Gate Array (FPGA) make it preferable in prototyping and implementation of different codes. This paper presents a survey on the current literatures that deals with FPGA-based decoder design associated with the previously mentioned channel codes

Towards Quantum Belief Propagation for LDPC Decoding in Wireless Networks

We present Quantum Belief Propagation (QBP), a Quantum Annealing (QA) based decoder design for Low Density Parity Check (LDPC) error control codes, which have found many useful applications in Wi-Fi, satellite communications, mobile cellular systems, and data storage systems. QBP reduces the LDPC decoding to a discrete optimization problem, then embeds that reduced design onto quantum annealing hardware. QBP's embedding design can support LDPC codes of block length up to 420 bits on real state-of-the-art QA hardware with 2,048 qubits. We evaluate performance on real quantum annealer hardware, performing sensitivity analyses on a variety of parameter settings. Our design achieves a bit error rate of $10^{-8}$ in 20 $\mu$s and a 1,500 byte frame error rate of $10^{-6}$ in 50 $\mu$s at SNR 9 dB over a Gaussian noise wireless channel. Further experiments measure performance over real-world wireless channels, requiring 30 $\mu$s to achieve a 1,500 byte 99.99$\%$ frame delivery rate at SNR 15-20 dB. QBP achieves a performance improvement over an FPGA based soft belief propagation LDPC decoder, by reaching a bit error rate of $10^{-8}$ and a frame error rate of $10^{-6}$ at an SNR 2.5--3.5 dB lower. In terms of limitations, QBP currently cannot realize practical protocol-sized ($\textit{e.g.,}$ Wi-Fi, WiMax) LDPC codes on current QA processors. Our further studies in this work present future cost, throughput, and QA hardware trend considerations

1.5 Gbit/s FPGA implementation of a fully-parallel turbo decoder designed for mission-critical machine-type communication applications

In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction. However, owing to the serial data dependencies imposed by the underlying Logarithmic Bahl-Cocke-Jelinek-Raviv (Log- BCJR) algorithm, the limited processing throughputs of conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of realtime wireless communication schemes. Motivated by this, we recently proposed a Fully Parallel Turbo Decoder (FPTD) algorithm, which eliminates these serial data dependencies, allowing parallel processing and hence offering a significantly higher processing throughput. In this paper, we propose a novel resource-efficient version of the FPTD algorithm, which reduces its computational resource requirement by 50%, which enhancing its suitability for Field-Programmable Gate Array (FPGA) implementations. We propose a model FPGA implementation. When using a Stratix IV FPGA, the proposed FPTD FPGA implementation achieves an average throughput of 1.53 Gbit/s and an average latency of 0.56 s, when decoding frames comprising N=720 bits. These are respectively 13.2 times and 11.1 times superior to those of the state-of-the- art FPGA implementation of the Log-BCJR Long- Term Evolution (LTE) turbo decoder, when decoding frames of the same frame length at the same error correction capability. Furthermore, our proposed FPTD FPGA implementation achieves a normalized resource usage of 0.42 kALUTs Mbit/s , which is 5.2 times superior to that of the benchmarker decoder. Furthermore, when decoding the shortest N=40-bit LTE frames, the proposed FPTD FPGA implementation achieves an average throughput of 442 Mbit/s and an average latency of 0.18 s, which are respectively 21.1 times and 10.6 times superior to those of the benchmarker decoder. In this case, the normalized resource usage of 0.08 kALUTs Mbit/s is 146.4 times superior to that of the benchmarker decoder

Low-Density Parity-Check Code Decoder Design and Error Characterization on an FPGA Based Framework

Low-Density Parity-Check (LDPC) codes have gained popularity in communication systems and standards due to their capacity approaching error correction performance. Among all the hard-decision based LDPC decoders, Gallager B (GaB), due to simplicity of its operations, poses as the most hardware friendly algorithm and an attractive solution for meeting the high-throughput demand in communication systems. However, GaB sufferers from poor error correction performance. In this work, we first propose a resource efficient GaB hardware architecture that delivers the best throughput while using fewest Field Programmable Gate Array (FPGA) resources with respect to the state of the art comparable LDPC decoding algorithms. We then introduce a Probabilistic GaB (PGaB) algorithm that disturbs the decisions made during the decoding iterations randomly with a probability value determined based on experimental studies. We achieve up to four orders of magnitude better error correction performance than the GaB with a 3.4% improvement in normalized throughput performance. PGaB requires around 40% less energy than GaB as the probabilistic execution results with reducing the average iteration count by up to 62% compared to the GaB. We also show that our PGaB consistently results with an improvement in maximum operational clock rate compared to the state of the art implementations. In this dissertation, we also present a high throughput FPGA based framework to accelerate error characterization of the LDPC codes. Our flexible framework allows the end user adjust the simulation parameters and rapidly study various LDPC codes and decoders. We first show that the connection intensive bipartite graph based LDPC decoder hardware architecture creates routing stress for longer codewords that are utilized in today's communications systems and standards. We address this problem by partitioning each processing element (PE) in the bipartite graph in such a way that the inputs of a PE are evenly distributed over its partitions. This allows depopulating the Loo Up Table (LUT) resources utilized for the decoder architecture by spreading the logic across the FPGA. We show that even though LUT usage increases, critical path delay reduces with the depopulation. More importantly, with the depopulation technique an unroutable design becomes routable, which allows longer codewords to be mapped on the FPGA. We then conduct two experiments on error correction performance analysis for the GaB and PGaB algorithms, demonstrate our framework's ability to reach a resolution level that is not attainable with general purpose processor (GPP) based simulations, which reduces the time scale of simulations to 24 hours from an estimated 199 years. We finally conduct the first study on identifying all possible codewords that are not correctable by the GaB for the case where a codeword has four errors. We reduce the time scale of this simulation that requires processing 117 billion codewords to 4 hours and 38 minutes with our framework from an estimated 7800 days on a single GPP