A Technique for Designing Variation Resilient Subthreshold Sram Cell

This paper presents a technique for designing a variability aware subthreshold SRAM cell. The architecture of the proposed cell is similar to the standard read-decoupled 8-transistor (RD8T) SRAM cell with the exception that the access FETS are replaced with transmission gates (TGs). In this work, various design metrics are assessed and compared with RD8T SRAM cell. The proposed design offers 2.14× and 1.75× improvement in TRA (read access time) and TWA (write access time) respectively compared with RD8T. It proves its robustness against process variations by featuring narrower spread in TRA distribution (2.35×) and TWA distribution (3.79×) compared with RD8T. The proposed bitcell offers 1.16× higher read current (IREAD) and 1.64× lower bitline leakage current (ILEAK) respectively compared with RD8T. It also shows its robustness by offering 1.34× (1.58×) tighter spread in IREAD (ILEAK) compared with RD8T. It exhibits 1.42× larger IREAD to ILEAK ratio. It shows 2.2× higher frequency @ 250 mV with read bitline capacitance of 10 fF. Besides, the proposed bitcell achieves same read stability and write-ability as that of RD8T at the cost of 3 extra transistors. The leakage power of the proposed design is close to that of RD8T.   ABSTRAK: Kertas kerja ini membentangkan teknik merekabentuk sel bawah ambang SRAM yang bolehubah. Senibina sel yang dicadangkan adalah sama dengan sel SRAM 8-transistor (RD8T) “pisahan-bacaan” piawai kecuali FET akses  digantikan dengan sel pintu transmisi (TGs). Di dalam kajian ini, beberapa metrik rekabentuk dinilai dan dibandingkan dengan sel RD8T SRAM. Rekabentuk yang dicadangkan menawarkan  peningkatan 2.14× dan 1.75×  dalam TRA (masa akses baca) dan TWA (masa akses tulis) berbanding dengan RD8T. Ia membuktikan kekukuhan variasi proses dengan menampilkan tebaran yang lebih sempit dalam pengagihan TRA (2.35 ×) dan pengagihan TWA (3.79 ×) berbanding dengan RD8T. Sel-Bit yang dicadangkan mempunyai arus baca 1.16 × lebih tinggi  (IREAD) dan arus bocor bitline 1.64 × lebih rendah (ILEAK) berbanding dengan RD8T. Ia juga membuktikan kekukuhan dengan menawarkan 1.34 × (1.58 ×) penyebaran sempit di IREAD (ILEAK) berbanding dengan RD8T dan nisbah IREAD / ILEAK 1.42 × lebih besar. Ia menunjukkan kekerapan 2.2 × lebih tinggi pada 250 mV dengan kemuatan membaca bitline sebanyak 10 fF. Selain itu, sel bit yang dicadangkan mencapai kestabilan membaca dan keupayaan menulis yang sama seperti RD8T dengan kos tambahan 3 transistor. Kebocoran kuasa  rekabentuk yang dicadangkan hampir sama dengan RD8T. KEYWORDS: variability; robust, subthreshold; random dopant fluctuation (RDF); read static noise margin (RSNM); write static noise margin (WSNM)

Performance analysis of 22NM FinFET-based 8T SRAM cell

As CMOS devices are approaching nanometer regime, there are a lot of consequences found in scaling down CMOS devices such as short channel effects and process variations which affect the reliability and performance of the devices. Researchers have found that FinFET is one of the outstanding nominee to overcome this issue since FinFET has better control over the channel and the lower overall capacitance which will increase the performance of the 6T Static Random Access Memory (SRAM) circuit design. It will help in reducing bitline loading and hence improve SRAM performance. The conventional 6T SRAM cell suffers serious stability degradation issue due to access disturbance at low power mode. The major problem in 6T SRAM is that, when the output voltage reduced below the threshold voltage of the transistor, it will destroy the read operation of the 6T SRAM cell. The noises are easy to destruct the stored-data in the nodes of the 6T SRAM cell due to the direct path between storage nodes and bit lines. To overcome this issue, an 8T SRAM cell has been proposed where the read stability is expected to improve. The purpose of this study is to simulate and evaluate the performance of FinFET-based 6T SRAM and 8T SRAM cell and compare their results. In 8T SRAM, the two additional access transistors eliminate the discharging path from RBL to ground in 6T SRAM cell which in turn help in improving the stability of read operation in 8T SRAM. The stability of SRAM cell is determined by the butterfly curve which is obtained by combining the voltage transfer curve (VTC) of the two cross-coupled inverters of the SRAM cell. GTS Framework TCAD tool is used to design and simulate the FinFET device structure, the schematic and the layout of SRAM cell. From the findings, the FinFET gives better Vth, DIBL, SS and ION than MOSFET. In addition, 6T and 8T FinFET-based SRAM cell have shown a better stability than 6T and 8T MOSFET-based SRAM cell in retention mode, read mode and write mode. Compared to FinFET-based 6T SRAM cell, FinFET-based 8T SRAM cell improved the read stability by 68.5% and not causing any degradation on the write and retention noise margin

6T CMOS SRAM Stability in Nanoelectronic Era: From Metrics to Built-in Monitoring

The digital technology in the nanoelectronic era is based on intensive data processing and battery-based devices. As a consequence, the need for larger and energy-efficient circuits with large embedded memories is growing rapidly in current system-on-chip (SoC). In this context, where embedded SRAM yield dominate the overall SoC yield, the memory sensitivity to process variation and aging effects has aggressively increased. In addition, long-term aging effects introduce extra variability reducing the failure-free period. Therefore, although stability metrics are used intensively in the circuit design phases, more accurate and non-invasive methodologies must be proposed to observe the stability metric for high reliability systems. This chapter reviews the most extended memory cell stability metrics and evaluates the feasibility of tracking SRAM cell reliability evolution implementing a detailed bit-cell stability characterization measurement. The memory performance degradation observation is focused on estimating the threshold voltage (Vth) drift caused by process variation and reliability mechanisms. A novel SRAM stability degradation measurement architecture is proposed to be included in modern memory designs with minimal hardware intrusion. The new architecture may extend the failure-free period by introducing adaptable circuits depending on the measured memory stability parameter

Estudo sobre os efeitos do Random Telegraph Noise em uma célula de memória SRAM 6T

O Random Telegraph Noise (RTN) causa variações no funcionamento de circuitos eletrônicos e tem sido cada vez mais expressivo em novas tecnologias. Assim, circuitos que visam um grande desempenho, uma menor área e um menor consumo de energia são os mais afetados. Um dos mais relevantes é a célula de memória SRAM. Por esse motivo, este trabalho visa desenvolver um estudo sobre os efeitos do RTN nesse importante circuito. Para isso, primeiramente foram computadas simulações mais simples, simulando os efeitos do ruído causando uma variação de tensão de limiar constante em grupos de transistores, com objetivo de demonstrar como o impacto do RTN nas tensões de threshold age para causar erros nas operações de uma célula de memória SRAM 6T. Depois, foram computadas análises de Monte Carlo. A primeira visa o estudo sobre as constantes de tempo do RTN. A segunda, uma análise sobre a dependência do número de erros causados na célula de memória em função de alguns dos principais parâmetros do Random Telegraph Noise: o impacto na tensão de limiar dos transistores e suas constantes de tempo. As simulações foram realizadas por meio do software NGSpice 2.4 e uma extensão a ele, desenvolvida no Laboratório de Prototipação e Testes (Laprot) da Universidade Federal do Rio Grande do Sul. Com os dados coletados foi possível a compreensão sobre as falhas causadas pelo RTN, a origem e a relevância.Random Telegraph Noise (RTN) causes variations in the functioning of integrated circuits and has been increasingly important in new technologies. Thus, circuits that aim at high performance, small area and lower power consumption are the most affected. One of the most relevant circuits is the SRAM memory cell. For this reason, this work aims to develop a study of the effects of RTN in this important circuit. For this, first, basic simulations were realized simulating the effects of the noise causing a constant threshold voltage variation in transistor groups in order to demonstrate how the impact of RTN on the threshold voltage acts to cause errors in the operations of a 6T SRAM memory cell. Then, Monte Carlo runs were performed. The first aims to study the RTN time constants. The second aims to analyze the dependence between the number of errors caused in the memory cell as a function of some of the main Random Telegraph Noise parameters: the impact on the threshold voltage on a single trap and their time constants. The simulations were performed using the NGSpice 2.4 software and an extension to it, developed at Laboratório de Prototipação e Testes (Laprot) of the Federal University of Rio Grande do Sul. With the collected data it was possible to understand the errors caused by the RTN, their causes and their relevance

Design of High Performance SRAM Based Memory Chip

The semiconductor memory SRAM uses bi-stable latch circuit to store the logic data 1 or 0. It differs from Dynamic RAM (DRAM) which needs periodic refreshment operation for the storage of logic data. Depending upon the frequency of operation SRAM power consumption varies i.e. it consumes very high power at higher frequencies like DRAM. The Cache memory present in the microprocessor needs high speed memory hence SRAM can be used for that purpose in microprocessors. The DRAM is normally used in the Main memory of processors, where importance is given to the density than its speed. The SRAM is also used in industrial subsystems, scientific and automotive electronics. In this thesis 16-Kb Memory is designed by using memory banking method in UMC 90nm technology ,which operates at a frequency of 1GHz.The post layout simulation for the complete design is performed and also obtained power analysis for the overall design. All peripherals like pre-charge, Row Decoder, Word line driver, Sense amplifier, Column Decoder/Mux and write driver are designed and layouts of all the above peripherals also drawn in an optimised manner such that their layout occupies minimum area. The 6T SRAM cell is designed with operating frequency of 8 GHz and stability analysis are also performed for single SRAM cell. The layout of Single SRAM cell is drawn in a symmetric manner, such that two adjacent cells can share same contact, which results reduction in the area of cell layout. The Static Noise Margin, Read noise margin and Write Noise Margin of single cell are found to be 240mV, 115mV and 425mV respectively for a supply voltage of 1V.The effect of pull-up ratio and cell ratio on the stability of SRAM cell is observed