47 research outputs found

    Area- and Energy- Efficient Modular Circuit Architecture for 1,024-Channel Parallel Neural Recording Microsystem.

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    This research focuses to develop system architectures and associated electronic circuits for a next generation neuroscience research tool, a massive-parallel neural recording system capable of recording 1,024 channels simultaneously. Three interdependent prototypes have been developed to address major challenges in realization of the massive-parallel neural recording microsystems: minimization of energy and area consumption while preserving high quality in recordings. First, a modular 128-channel Δ-ΔΣ AFE using the spectrum shaping has been designed and fabricated to propose an area-and energy efficient solution for neural recording AFEs. The AFE achieved 4.84 fJ/C−s·mm2 figure of merit that is the smallest the area-energy product among the state-of-the-art multichannel neural recording systems. It also features power and area consumption of 3.05 ”W and 0.05 mm2 per channel, respectively while exhibiting 63.3 dB signal-to-noise ratio with 3.02 ”Vrms input referred noise. Second, an on-chip mixed signal neural signal compressor was built to reduce the energy consumption in handling and transmission of the recorded data since this occupies a large portion of the total energy consumption as the number of parallel recording increases. The compressor reduces the data rates of two distinct groups of neural signals that are essential for neuroscience research: LFP and AP without loss of informative signals. As a result, the power consumptions for the data handling and transmissions of the LFP and AP were reduced to about 1/5.35 and 1/10.54 of the uncompressed cases, respectively. In the total data handling and transmission, the measured power consumption per channel is 11.98 ”W that is about 1/9 of 107.5 ”W without the compression. Third, a compact on-chip dc-to-dc converter with constant 1 MHz switching frequency has been developed to provide reliable power supplies and enhance energy delivery efficiency to the massive-parallel neural recording systems. The dc-to-dc converter has only predictable tones at the output and it exhibits > 80% power conversion efficiency at ultra-light loads, < 100 ”W that is relevant power most of the multi-channel neural recording systems consume. The dc-to-dc converter occupies 0.375 mm2 of area which is less than 1/20 of the area the first prototype consumes (8.64 mm2).PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133244/1/sungyun_1.pd

    An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mmÂČ Ă— fJ/conv-step Efficiency and 0.97 NEF

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    This letter presents an energy-and-area-efficient ac-coupled front-end for the multichannel recording of wideband neural signals. The proposed unit conditions local field and action potentials using an inverter-based capacitively coupled low-noise amplifier, followed by a per-channel 10-b asynchronous SAR ADC. The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated. The prototype in 65-nm CMOS achieves 4× smaller area and 3× higher energy–area efficiency compared to the state of the art with 164 ÎŒm×40ÎŒm footprint and 0.78 mmÂČ× fJ/conv-step energy-area figure of merit. The measured 0.65- ÎŒW power consumption and 3.1 - ÎŒVrms input-referred noise within 1 Hz–10 kHz bandwidth correspond to a noise efficiency factor of 0.97

    An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mmÂČ Ă— fJ/conv-step Efficiency and 0.97 NEF

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    This letter presents an energy-and-area-efficient ac-coupled front-end for the multichannel recording of wideband neural signals. The proposed unit conditions local field and action potentials using an inverter-based capacitively coupled low-noise amplifier, followed by a per-channel 10-b asynchronous SAR ADC. The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated. The prototype in 65-nm CMOS achieves 4× smaller area and 3× higher energy–area efficiency compared to the state of the art with 164 ÎŒm×40ÎŒm footprint and 0.78 mmÂČ× fJ/conv-step energy-area figure of merit. The measured 0.65- ÎŒW power consumption and 3.1 - ÎŒVrms input-referred noise within 1 Hz–10 kHz bandwidth correspond to a noise efficiency factor of 0.97

    Towards Neuromorphic Compression based Neural Sensing for Next-Generation Wireless Implantable Brain Machine Interface

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    This work introduces a neuromorphic compression based neural sensing architecture with address-event representation inspired readout protocol for massively parallel, next-gen wireless iBMI. The architectural trade-offs and implications of the proposed method are quantitatively analyzed in terms of compression ratio and spike information preservation. For the latter, we use metrics such as root-mean-square error and correlation coefficient between the original and recovered signal to assess the effect of neuromorphic compression on spike shape. Furthermore, we use accuracy, sensitivity, and false detection rate to understand the effect of compression on downstream iBMI tasks, specifically, spike detection. We demonstrate that a data compression ratio of 50−10050-100 can be achieved, 5−18×5-18\times more than prior work, by selective transmission of event pulses corresponding to neural spikes. A correlation coefficient of ≈0.9\approx0.9 and spike detection accuracy of over 90%90\% for the worst-case analysis involving 10K10K-channel simulated recording and typical analysis using 100100 or 384384-channel real neural recordings. We also analyze the collision handling capability and scalability of the proposed pipeline.Comment: 14 pages, 8 figures, IEEE Transaction submission manuscript. This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessibl

    An electronic neuromorphic system for real-time detection of High Frequency Oscillations (HFOs) in intracranial EEG

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    In this work, we present a neuromorphic system that combines for the first time a neural recording headstage with a signal-to-spike conversion circuit and a multi-core spiking neural network (SNN) architecture on the same die for recording, processing, and detecting High Frequency Oscillations (HFO), which are biomarkers for the epileptogenic zone. The device was fabricated using a standard 0.18Ό\mum CMOS technology node and has a total area of 99mm2^{2}. We demonstrate its application to HFO detection in the iEEG recorded from 9 patients with temporal lobe epilepsy who subsequently underwent epilepsy surgery. The total average power consumption of the chip during the detection task was 614.3Ό\muW. We show how the neuromorphic system can reliably detect HFOs: the system predicts postsurgical seizure outcome with state-of-the-art accuracy, specificity and sensitivity (78%, 100%, and 33% respectively). This is the first feasibility study towards identifying relevant features in intracranial human data in real-time, on-chip, using event-based processors and spiking neural networks. By providing "neuromorphic intelligence" to neural recording circuits the approach proposed will pave the way for the development of systems that can detect HFO areas directly in the operation room and improve the seizure outcome of epilepsy surgery.Comment: 16 pages. A short video describing the rationale underlying the study can be viewed on https://youtu.be/NuAA91fdma

    Resource-Constrained Acquisition Circuits for Next Generation Neural Interfaces

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    The development of neural interfaces allowing the acquisition of signals from the cortex of the brain has seen an increasing amount of interest both in academic research as well as in the commercial space due to their ability to aid people with various medical conditions, such as spinal cord injuries, as well as their potential to allow more seamless interactions between people and machines. While it has already been demonstrated that neural implants can allow tetraplegic patients to control robotic arms, thus to an extent returning some motoric function, the current state of the art often involves the use of heavy table-top instruments connected by wires passing through the patient’s skull, thus making the applications impractical and chronically infeasible. Those limitations are leading to the development of the next generation of neural interfaces that will overcome those issues by being minimal in size and completely wireless, thus paving a way to the possibility of their chronic application. Their development however faces several challenges in numerous aspects of engineering due to constraints presented by their minimal size, amount of power available as well as the materials that can be utilised. The aim of this work is to explore some of those challenges and investigate novel circuit techniques that would allow the implementation of acquisition analogue front-ends under the presented constraints. This is facilitated by first giving an overview of the problematic of recording electrodes and their electrical characterisation in terms of their impedance profile and added noise that can be used to guide the design of analogue front-ends. Continuous time (CT) acquisition is then investigated as a promising signal digitisation technique alternative to more conventional methods in terms of its suitability. This is complemented by a description of practical implementations of a CT analogue-to-digital converter (ADC) including a novel technique of clockless stochastic chopping aimed at the suppression of flicker noise that commonly affects the acquisition of low-frequency signals. A compact design is presented, implementing a 450 nW, 5.5 bit ENOB CT ADC, occupying an area of 0.0288 mm2 in a 0.18 ÎŒm CMOS technology, making this the smallest presented design in literature to the best of our knowledge. As completely wireless neural implants rely on power delivered through wireless links, their supply voltage is often subject to large high frequency variations as well voltage uncertainty making it necessary to design reference circuits and voltage regulators providing stable reference voltage and supply in the constrained space afforded to them. This results in numerous challenges that are explored and a design of a practical implementation of a reference circuit and voltage regulator is presented. Two designs in a 0.35 ÎŒm CMOS technology are presented, showing respectively a measured PSRR of ≈60 dB and ≈53 dB at DC and a worst-case PSRR of ≈42 dB and ≈33 dB with a less than 1% standard deviation in the output reference voltage of 1.2 V while consuming a power of ≈7 ÎŒW. Finally, ΣΔ modulators are investigated for their suitability in neural signal acquisition chains, their properties explained and a practical implementation of a ΣΔ DC-coupled neural acquisition circuit presented. This implements a 10-kHz, 40 dB SNDR ΣΔ analogue front-end implemented in a 0.18 ÎŒm CMOS technology occupying a compact area of 0.044 ÎŒm2 per channel while consuming 31.1 ÎŒW per channel.Open Acces

    Interfaces neuronales CMOS haute résolution pour l'électrophysiologie et l'optogénétique en boucle fermée

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    L’avenir de la recherche sur les maladies du cerveau repose sur le dĂ©veloppement de nouvelles technologies qui permettront de comprendre comment cet organe si complexe traite, intĂšgre et transfĂšre l’information. Parmi celles-ci, l’optogĂ©nĂ©tique est une technologie rĂ©volutionnaire qui permet d’utiliser de la lumiĂšre afin d’activer sĂ©lectivement les neurones du cortex d’animaux transgĂ©niques pour observer leur effet dans un vaste rĂ©seau biologique. Ce cadre expĂ©rimental repose typiquement sur l’observation de l’activitĂ© neuronale de souris transgĂ©niques, car elles peuvent exprimer une grande variĂ©tĂ© de gĂšnes et de maladies et qu’elles sont peu couteuses. Toutefois, la plupart des appareils de mesure ou de stimulation optogĂ©nĂ©tique disponible ne sont pas appropriĂ©s, car ils sont cĂąblĂ©s, trop lourds et/ou trop simplistes. Malheureusement, peu de systĂšmes sans fil existent, et ces derniers sont grandement limitĂ©s par la bande passante requise pour transmettre les donnĂ©es neuronales, et ils ne fournissent pas de stimulation optogĂ©nĂ©tique multicanal afin de stimuler et observer plusieurs rĂ©gions du cerveau. Dans les dispositifs actuels, l’interprĂ©tation des donnĂ©es neuronales est effectuĂ©e ex situ, alors que la recherche bĂ©nĂ©ficierait grandement de systĂšmes sans fil assez intelligents pour interprĂ©ter et stimuler les neurones en boucle fermĂ©e, in situ. Le but de ce projet de recherche est de concevoir des circuits analogiques-numĂ©riques d’acquisition et de traitement des signaux neuronaux, des algorithmes d’analyse et de traitement de ces signaux et des systĂšmes electro-optiques miniatures et sans fil pour : i) Mener des expĂ©riences combinant l’enregistrement neuronal et l’optogĂ©nĂ©tique multicanal haute rĂ©solution avec des animaux libres de leurs mouvements. ii) Mener des expĂ©riences optogĂ©nĂ©tiques synchronisĂ©es avec l’observation, c.-Ă -d. en boucle fermĂ©e, chez des animaux libres de leurs mouvements. iii) RĂ©duire la taille, le poids et la consommation Ă©nergĂ©tique des systĂšmes optogĂ©nĂ©tiques sans fil afin de minimiser l’impact de la recherche chez de petits animaux. Ce projet est en 3 phases, et ses principales contributions ont Ă©tĂ© rapportĂ©es dans dix confĂ©rences internationales (ISSCC, ISCAS, EMBC, etc.) et quatre articles de journaux publiĂ©s ou soumis, ainsi que dans un brevet et deux divulgations. La conception d’un systĂšme optogĂ©nĂ©tique haute rĂ©solution pose plusieurs dĂ©fis importants. Notamment, puisque les signaux neuronaux ont un contenu frĂ©quentiel Ă©levĂ© (_10 kHz), le nombre de canaux sous observation est limitĂ© par la bande passante des transmetteurs sans fil (2-4 canaux en gĂ©nĂ©ral). Ainsi, la premiĂšre phase du projet a visĂ© le dĂ©veloppement d’algorithmes de compression des signaux neuronaux et leur intĂ©gration dans un systĂšme optogĂ©nĂ©tique sans fil miniature et lĂ©ger (2.8 g) haute rĂ©solution possĂ©dant 32 canaux d’acquisition et 32 canaux de stimulation optique. Le systĂšme dĂ©tecte, compresse et transmet les formes d’onde des potentiels d’action (PA) produits par les neurones avec un field programmable gate array (FPGA) embarquĂ© Ă  faible consommation Ă©nergĂ©tique. Ce processeur implĂ©mente un algorithme de dĂ©tection des PAs basĂ© sur un seuillage adaptatif, ce qui permet de compresser les signaux en transmettant seulement les formes dĂ©tectĂ©es. Chaque PA est davantage compressĂ© par une transformĂ©e en ondelette discrĂšte (DWT) de type Symmlet-2 suivie d’une technique de discrimination et de requantification dynamique des coefficients. Les rĂ©sultats obtenus dĂ©montrent que cet algorithme est plus robuste que les mĂ©thodes existantes tout en permettant de reconstruire les signaux compressĂ©s avec une meilleure qualitĂ© (SNDR moyen de 25 dB _ 5% pour un taux de compression (CR) de 4.2). Avec la dĂ©tection, des CR supĂ©rieurs Ă  500 sont rapportĂ©s lors de la validation in vivo. L’utilisation de composantes commerciales dans des systĂšmes optogĂ©nĂ©tiques sans fil augmentela taille et la consommation Ă©nergĂ©tique, en plus de ne pas ĂȘtre optimisĂ©e pour cette application. La seconde phase du projet a permis de concevoir un systĂšme sur puce (SoC) complementary metal oxide semiconductor (CMOS) pour faire de l’enregistrement neuronal et de optogĂ©nĂ©tique multicanal, permettant de rĂ©duire significativement la taille et la consommation Ă©nergĂ©tique comparativement aux alternatives commerciales. Ceci est une contribution importante, car c’est la premiĂšre puce Ă  ĂȘtre dotĂ© de ces deux fonctionnalitĂ©s. Le SoC possĂšde 10 canaux d’enregistrement et 4 canaux de stimulation optogĂ©nĂ©tique. La conception du bioamplificateur inclut une bande passante programmable (0.5 Hz - 7 kHz) et un faible bruit referrĂ© Ă  l’entrĂ© (IRN de 3.2 ÎŒVrms), ce qui permet de cibler diffĂ©rents types de signaux biologiques (PA, LFP, etc.). Le convertisseur analogique numĂ©rique (ADC) de type Delta- Sigma (DS) MASH 1-1-1 est conçu pour fonctionner de faibles taux de sur-Ă©chantillonnage (OSR _50) pour rĂ©duire sa consommation et possĂšde une rĂ©solution programmable (ENOB de 9.75 Bits avec un OSR de 25). Cet ADC exploite une nouvelle technique rĂ©duisant la taille du circuit en soustrayant la sortie de chaque branche du DS dans le domaine numĂ©rique, comparativement Ă  la mĂ©thode analogique classique. La consommation totale d’un canal d’enregistrement est de 11.2 ÎŒW. Le SoC implĂ©mente un nouveau circuit de stimulation optique basĂ© sur une source de courant de type cascode avec rĂ©troaction, ce qui permet d’accommoder une large gamme de LED et de tensions de batterie comparativement aux circuits existants. Le SoC est intĂ©grĂ© dans un systĂšme optogĂ©nĂ©tique sans fil et validĂ© in vivo. À ce jour et en excluant ce projet, aucun systĂšme sans-fil ne fait de l’optogĂ©nĂ©tique en boucle fermĂ©e simultanĂ©ment au suivi temps rĂ©el de l’activitĂ© neuronale. Une contribution importante de ce travail est d’avoir dĂ©veloppĂ© le premier systĂšme optogĂ©nĂ©tique multicanal qui est capable de fonctionner en boucle fermĂ©e et le premier Ă  ĂȘtre validĂ© lors d’expĂ©riences in vivo impliquant des animaux libres de leurs mouvements. Pour ce faire, la troisiĂšme phase du projet a visĂ© la conception d’un SoC CMOS numĂ©rique, appelĂ© neural decoder integrated circuit (ND-IC). Le ND-IC et le SoC dĂ©veloppĂ© lors de la phase 2 ont Ă©tĂ© intĂ©grĂ©s dans un systĂšme optogĂ©nĂ©tique sans fil. Le ND-IC possĂšde 3 modules : 1) le dĂ©tecteur de PA adaptatif, 2) le module de compression possĂ©dant un nouvel arbre de tri pour discriminer les coefficients, et 3) le module de classement automatique des PA qui rĂ©utilise les donnĂ©es gĂ©nĂ©rĂ©es par le module de dĂ©tection et de compression pour rĂ©duire sa complexitĂ©. Un lien entre un canal d’enregistrement et un canal de stimulation est Ă©tabli selon l’association de chaque PA Ă  un neurone, grĂące Ă  la classification, et selon l’activitĂ© de ce neurone dans le temps. Le ND-IC consomme 56.9 ÎŒW et occupe 0.08 mm2 par canal. Le systĂšme pĂšse 1.05 g, occupe un volume de 1.12 cm3, possĂšde une autonomie de 3h, et est validĂ© in vivo.The future of brain research lies in the development of new technologies that will help understand how this complex organ processes, integrates and transfers information. Among these, optogenetics is a recent technology that allows the use of light to selectively activate neurons in the cortex of transgenic animals to observe their effect in a large biological network. This experimental setting is typically based on observing the neuronal activity of transgenic mice, as they express a wide variety of genes and diseases, while being inexpensive. However, most available neural recording or optogenetic devices are not suitable, because they are hard-wired, too heavy and/or too simplistic. Unfortunately, few wireless systems exist, and they are greatly limited by the required bandwidth to transmit neural data, while not providing simultaneous multi-channel neural recording and optogenetic, a must for stimulating and observing several areas of the brain. In current devices, the analysis of the neuronal data is performed ex situ, while the research would greatly benefit from wireless systems that are smart enough to interpret and stimulate the neurons in closed-loop, in situ. The goal of this project is to design analog-digital circuits for acquisition and processing of neural signals, algorithms for analysis and processing of these signals and miniature electrooptical wireless systems for: i) Conducting experiments combining high-resolution multi-channel neuronal recording and high-resolution multi-channel optogenetics with freely-moving animals. ii) Conduct optogenetic experiments synchronized with the neural recording, i.e. in closed loop, with freely-moving animals. iii) Increase the resolution while reducing the size, weight and energy consumption of the wireless optogenetic systems to minimize the impact of research with small animals. This project is in 3 phases, and its main contributions have been reported in ten conferences (ISSCC, ISCAS, EMBC, etc.) and four published journal papers, or submitted, as well as in a patent and two disclosures. The design of a high resolution optogenetic system poses several challenges. In particular, since the neuronal signals have a high frequency content (10 kHz), the number of chanv nels under observation is limited by the bandwidth of the wireless transmitters (2-4 channels in general). Thus, the first phase of the project focused on the development of neural signal compression algorithms and their integration into a high-resolution miniature and lightweight wireless optogenetics system (2.8g), having 32 recording channels and 32 optical stimulation channels. This system detects, compresses and transmits the waveforms of the signals produced by the neurons, i.e. action potentials (AP), in real time, via an embedded low-power field programmable gate array (FPGA). This processor implements an AP detector algorithm based on adaptive thresholding, which allows to compress the signals by transmitting only the detected waveforms. Each AP is further compressed by a Symmlet-2 discrete wavelet transform (DWT) followed dynamic discrimination and requantification of the DWT coefficients, making it possible to achieve high compression ratios with a good reconstruction quality. Results demonstrate that this algorithm is more robust than existing approach, while allowing to reconstruct the compressed signals with better quality (average SNDR of 25 dB 5% for a compression ratio (CR) of 4.2). With detection, CRs greater than 500 are reported during the in vivo validation. The use of commercial components in wireless optogenetic systems increases the size and power consumption, while not being optimized for this application. The second phase of the project consisted in designing a complementary metal oxide semiconductor (CMOS) system-on-chip (SoC) for neural recording and multi-channel optogenetics, which significantly reduces the size and energy consumption compared to commercial alternatives. This is important contribution, since it’s the first chip to integrate both features. This SoC has 10 recording channels and 4 optogenetic stimulation channels. The bioamplifier design includes a programmable bandwidth (0.5 Hz -7 kHz) and a low input-referred noise (IRN of 3.2 ÎŒVrms), which allows targeting different biological signals (AP, LFP, etc.). The Delta-Sigma (DS) MASH 1-1-1 low-power analog-to-digital converter (ADC) is designed to work with low OSR (50), as to reduce its power consumption, and has a programmable resolution (ENOB of 9.75 bits with an OSR of 25). This ADC uses a new technique to reduce its circuit size by subtracting the output of each DS branch in the digital domain, rather than in the analog domain, as done conventionally. A recording channel, including the bioamplifier, the DS and the decimation filter, consumes 11.2 ÎŒW. Optical stimulation is performed with an on-chip LED driver using a regulated cascode current source with feedback, which accommodates a wide range of LED parameters and battery voltages. The SoC is integrated into a wireless optogenetic platform and validated in vivo.To date and excluding this project, no wireless system is making closed-loop optogenetics simultaneously to real-time monitoring of neuronal activity. An important contribution of this work is to have developed the first multi-channel optogenetic system that is able to work in closed-loop, and the first to be validated during in vivo experiments involving freely-moving animals. To do so, the third phase of the project aimed to design a digital CMOS chip, called neural decoder integrated circuit (ND-IC). The ND-IC and the SoC developed in Phase 2 are integrated within a wireless optogenetic system. The ND-IC has 3 main cores: 1) the adaptive AP detector core, 2) the compression core with a new sorting tree for discriminating the DWT coefficients, and 3 ) the AP automatic classification core that reuses the data generated by the detection and compression cores to reduce its complexity. A link between a recording channel and a stimulation channel is established according to the association of each AP with a neuron, thanks to the classification, and according to the bursting activity of this neuron. The ND-IC consumes 56.9 ÎŒW and occupies 0.08 mm2 per channel. The system weighs 1.05 g, occupies a volume of 1.12 cm3, has an autonomy of 3h, and is validated in vivo

    Wearable electroencephalography for long-term monitoring and diagnostic purposes

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    Truly Wearable EEG (WEEG) can be considered as the future of ambulatory EEG units, which are the current standard for long-term EEG monitoring. Replacing these short lifetime, bulky units with long-lasting, miniature and wearable devices that can be easily worn by patients will result in more EEG data being collected for extended monitoring periods. This thesis presents three new fabricated systems, in the form of Application Specific Integrated Circuits (ASICs), to aid the diagnosis of epilepsy and sleep disorders by detecting specific clinically important EEG events on the sensor node, while discarding background activity. The power consumption of the WEEG monitoring device incorporating these systems can be reduced since the transmitter, which is the dominating element in terms of power consumption, will only become active based on the output of these systems. Candidate interictal activity is identified by the developed analog-based interictal spike selection system-on-chip (SoC), using an approximation of the Continuous Wavelet Transform (CWT), as a bandpass filter, and thresholding. The spike selection SoC is fabricated in a 0.35 ÎŒm CMOS process and consumes 950 nW. Experimental results reveal that the SoC is able to identify 87% of interictal spikes correctly while only transmitting 45% of the data. Sections of EEG data containing likely ictal activity are detected by an analog seizure selection SoC using the low complexity line length feature. This SoC is fabricated in a 0.18 ÎŒm CMOS technology and consumes 1.14 ÎŒW. Based on experimental results, the fabricated SoC is able to correctly detect 83% of seizure episodes while transmitting 52% of the overall EEG data. A single-channel analog-based sleep spindle detection SoC is developed to aid the diagnosis of sleep disorders by detecting sleep spindles, which are characteristic events of sleep. The system identifies spindle events by monitoring abrupt changes in the input EEG. An approximation of the median frequency calculation, incorporated as part of the system, allows for non-spindle activity incorrectly identified by the system as sleep spindles to be discarded. The sleep spindle detection SoC is fabricated in a 0.18 ÎŒm CMOS technology, consuming only 515 nW. The SoC achieves a sensitivity and specificity of 71.5% and 98% respectively.Open Acces

    A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System

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    This paper presents a low-power, low-noise microsystem for the recording of neural local field potentials or intracranial electroencephalographic signals. It features 32 time-multiplexed channels at the electrode interface and offers the possibility to spatially delta encode data to take advantage of the large correlation of signals captured from nearby channels. The circuit also implements a mixed-signal voltage-triggered auto-ranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information. This effectively increases the system dynamic range and avoids the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro with cellular cultures of primary cortical neurons from mice. The system shows an integrated input-referred noise in the 0.5–200 Hz band of 1.4 ”Vrms for a spot noise of about 85 nV / √Hz. The system draws 1.5 ”W per channel from 1.2 V supply and obtains 71 dB + 26 dB dynamic range when the artifact-aware auto-ranging mechanism is enabled, without penalising other critical specifications such as crosstalk between channels or common-mode and power supply rejection ratios

    Nano-Watt Modular Integrated Circuits for Wireless Neural Interface.

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    In this work, a nano-watt modular neural interface circuit is proposed for ECoG neuroprosthetics. The main purposes of this work are threefold: (1) optimizing the power-performance of the neural interface circuits based on ECoG signal characteristics, (2) equipping a stimulation capability, and (3) providing a modular system solution to expand functionality. To achieve these aims, the proposed system introduces the following contributions/innovations: (1) power-noise optimization based on the ECoG signal driven analysis, (2) extreme low-power analog front-ends, (3) Manchester clock-edge modulation clock data recovery, (4) power-efficient data compression, (5) integrated stimulator with fully programmable waveform, (6) wireless signal transmission through skin, and (7) modular expandable design. Towards these challenges and contributions, three different ECoG neural interface systems, ENI-1, ENI-16, and ENI-32, have been designed, fabricated, and tested. The first ENI system(ENI-1) is a one-channel analog front-end and fabricated in a 0.25”m CMOS process with chopper stabilized pseudo open-loop preamplifier and area-efficient SAR ADC. The measured channel power, noise and area are 1.68”W at 2.5V power-supply, 1.69”Vrms (NEF=2.43), and 0.0694mm^2, respectively. The fabricated IC is packaged with customized miniaturized package. In-vivo human EEG is successfully measured with the fabricated ENI-1-IC. To demonstrate a system expandability and wireless link, ENI-16 IC is fabricated in 0.25”m CMOS process and has sixteen channels with a push-pull preamplifier, asynchronous SAR ADC, and intra-skin communication(ISCOM) which is a new way of transmitting the signal through skin. The measured channel power, noise and area are 780nW, 4.26”Vrms (NEF=5.2), and 2.88mm^2, respectively. With the fabricated ENI-16-IC, in-vivo epidural ECoG from monkey is successfully measured. As a closed-loop system, ENI-32 focuses on optimizing the power performance based on a bio-signal property and integrating stimulator. ENI-32 is fabricated in 0.18”m CMOS process and has thirty-two recording channels and four stimulation channels with a cyclic preamplifier, data compression, asymmetric wireless transceiver (Tx/Rx). The measured channel power, noise and area are 140nW (680nW including ISCOM), 3.26”Vrms (NEF=1.6), and 5.76mm^2, respectively. The ENI-32 achieves an order of magnitude power reduction while maintaining the system performance. The proposed nano-watt ENI-32 can be the first practical wireless closed-loop solution with a practically miniaturized implantable device.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98064/1/schang_1.pd
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