Jerarquía de memoria para instrucciones y cálculo del WCET

Uno de los principales retos de los sistemas de tiempo real es el cálculo del tiempo de ejecución del peor caso (WCET/Worst Case Execution Time), es decir, determinar el tiempo de ejecución del camino más largo. El cálculo del WCET tiene que ser seguro y también preciso, ya que la planificabilidad del sistema debe estar garantizada antes de su ejecución. El mercado de los sistemas de tiempo real añade una restricción importante en el diseño de la jerarquía de memoria, la necesidad de conocer un límite máximo del tiempo de ejecución, ya que este tiempo depende en gran medida del número máximo de fallos de cache que se producirán durante la ejecución. Pero, el análisis del comportamiento temporal en el peor caso de la cache es complejo, por lo tanto los diseñadores de sistemas de tiempo real descartan su utilización. En esta Tesis se analiza el comportamiento en el peor caso de varias jerarquías de memoria para instrucciones. En concreto se estudia, tanto una cache de instrucciones convencional, como una cache que pueda fijar su contenido. El principal objetivo de este análisis es conseguir el mejor rendimiento, en un sistema de tiempo real, de la jerarquía de memoria estudiada. Así pues, también se presentan diferentes técnicas de análisis y cálculo del WCET para cada una de las jerarquías de memoria estudiadas. Para una cache de instrucciones convencional con algoritmo de reemplazo LRU, analizamos su comportamiento en el peor caso y demostramos que el número de caminos relevantes generado por estructuras condicionales dentro de bucles no depende del número de iteraciones del bucle, sino que depende del número de caminos del condicional. Esto permite obtener la contribución exacta al WCET de los accesos a memoria, cuando el número de caminos condicionales dentro de un bucle no es grande. Así pues, proponemos una técnica para determinar la contribución exacta al WCET de los accesos a memoria. A esta técnica la denominamos poda dinámica de caminos. Estudiamos una jerarquía de memoria formada por un LB (Line Buffer) y una cache que pueda fijar su contenido (Lockable iCache). Para esta jerarquía de memoria proponemos un algoritmo óptimo que selecciona las líneas a fijar en la cache durante la ejecución de cada tarea del sistema. A este algoritmo lo hemos denominado Lock-MS (Lock for Maximize Schedulability). Además, proponemos una nueva jerarquía de memoria en sistemas de tiempo real con hardware de prebúsqueda secuencial (PB/Prefetch Buffer) y analizamos su influencia en el WCET de cada tarea. El LB y el PB capturan muy bien la localidad espacial y reducen considerablemente el WCET de las tareas. También permiten reducir la capacidad de la Lockable iCache sin comprometer la planificabilidad del sistema. Dado un conjunto de tareas que podrían formar un sistema de tiempo real, para cada una de las jerarquías de memoria analizadas, proponemos técnicas de análisis y cálculo del WCET totalmente seguro y más preciso que el obtenido con las técnicas de análisis ya descritas en la literatura. Finalmente, también se presenta un estudio sobre el consumo energético de una jerarquía de memoria formada por un LB, un PB y una Lockable iCache. Los resultados de este estudio indican que el camino del WCET de una tarea no coincide con el camino del WCEC (Worst Case Energy Consumption) de dicha tarea

Development of a hybrid power management unit for mobile applications: solar energy case study

Applying photovoltaic power to mobile devices has become a hot area of research due to the availability of solar energy. Usage of photovoltaic as the power source for mobile devices will enhance device performance. There are many challenges to interface photovoltaic energy to mobile loads such as variation of power coming out from photovoltaic panels, unregulated voltage and limited power. Maximum power point tracking (MPPT) is used in photovoltaic systems to maximize the photovoltaic array output power under environmental variations such as irradiation and temperature for mobile applications. A power management system is proposed to apply photovoltaic harvested energy effectively to mobile or handheld devices while running workloads. The proposed system mainly consists of a MPPT block and a Power Distribution Control Unit (PDCU). The PDCU allows usage of an AC/DC external in case of insufficient photovoltaic power in order to maintain the load running. Different cases of operation are handled by the PDCU unit depending on the availability of photovoltaic power, load power, battery state of charge and existence of the AC/DC external. In addition, a new MPPT algorithm is proposed to provide fast and accurate tracking. Analysis and simulation results are provided to demonstrate system functionality and performance sensitivity. Moreover, a prototype of the proposed system is still under progress, to verify the possibility of building such system

Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques

The fully synchronous approach has been the norm for digital signal processors (DSPs) for many decades. Due to its simplicity, the classical DSP structure has been used in many applications. However, due to its rigid discrete-time operation, a classical DSP has limited efficiency or inadequate resolution for some emerging applications, such as processing of multimedia and biological signals. This thesis proposes fundamentally new approaches to designing DSPs, which are different from the classical scheme. The defining characteristic of all new DSPs examined in this thesis is the notion of "adaptivity" or "adaptability." Adaptive DSPs dynamically change their behavior to adjust to some property of their input stream, for example the rate of change of the input. This thesis presents both enhancements to existing adaptive DSPs, as well as new adaptive DSPs. The main class of DSPs that are examined throughout the thesis are continuous-time (CT) DSPs. CT DSPs are clock-less and event-driven; they naturally adapt their activity and power consumption to the rate of their inputs. The absence of a clock also provides a complete avoidance of aliasing in the frequency domain, hence improved signal fidelity. The core of this thesis deals with the complete and systematic design of a truly general-purpose CT DSP. A scalable design methodology for CT DSPs is presented. This leads to the main contribution of this thesis, namely a new CT DSP chip. This chip is the first general-purpose CT DSP chip, able to process many different classes of CT and synchronous signals. The chip has the property of handling various types of signals, i.e. various different digital modulations, both synchronous and asynchronous, without requiring any reconfiguration; such property is presented for the first time CT DSPs and is impossible for classical DSPs. As opposed to previous CT DSPs, which were limited to using only one type of digital format, and whose design was hard to scale for different bandwidths and bit-widths, this chip has a formal, robust and scalable design, due to the systematic usage of asynchronous design techniques. The second contribution of this thesis is a complete methodology to design adaptive delay lines. In particular, it is shown how to make the granularity, i.e. the number of stages, adaptive in a real-time delay line. Adaptive granularity brings about a significant improvement in the line's power consumption, up to 70% as reported by simulations on two design examples. This enhancement can have a direct large power impact on any CT DSP, since a delay line consumes the majority of a CT DSP's power. The robust methodology presented in this thesis allows safe dynamic reconfiguration of the line's granularity, on-the-fly and according to the input traffic. As a final contribution, the thesis also examines two additional DSPs: one operating the CT domain and one using the companding technique. The former operates only on level-crossing samples; the proposed methodology shows a potential for high-quality outputs by using a complex interpolation function. Finally, a companding DSP is presented for MPEG audio. Companding DSPs adapt their dynamic range to the amplitude of their input; the resulting can offer high-quality outputs even for small inputs. By applying companding to MPEG DSPs, it is shown how the DSP distortion can be made almost inaudible, without requiring complex arithmetic hardware

Prosiding Seminar Nasional Pendidikan Teknik Elektro (SNPTE) 2013

Seminar Nasional Pendidikan Teknik Elektro (SNPTE) 2013 ini diselenggarakan sebagai wahana bagi akademisi, peneliti, praktisi, asosiasi, industri dan pengambil kebijakan untuk bisa saling bertukar pikiran, bertukar pendapat, mempresentasikan pengalaman-pengalaman hasil penelitian maupun hasil kajian di bidang Pendidikan dan Teknologi Elektro. Tema dalam SNPTE 2013 ini adalah "Peningkatan Mutu Pendidikan Kejuruan Mengacu Kerangka Kualifikasi Nasional Indonesia (KKNI)"