The 30-cm ion thruster power processor

A power processor unit for powering and controlling the 30 cm Mercury Electron-Bombardment Ion Thruster was designed, fabricated, and tested. The unit uses a unique and highly efficient transistor bridge inverter power stage in its implementation. The system operated from a 200 to 400 V dc input power bus, provides 12 independently controllable and closely regulated dc power outputs, and has an overall power conditioning capacity of 3.5 kW. Protective circuitry was incorporated as an integral part of the design to assure failure-free operation during transient and steady-state load faults. The implemented unit demonstrated an electrical efficiency between 91.5 and 91.9 at its nominal rated load over the 200 to 400 V dc input bus range

Definition study for photovoltaic residential prototype system

A site evaluation was performed to assess the relative merits of different regions of the country in terms of the suitability for experimental photovoltaic powered residences. Eight sites were selected based on evaluation criteria which included population, photovoltaic systems performance and the cost of electrical energy. A parametric sensitivity analysis was performed for four selected site locations. Analytical models were developed for four different power system implementation approaches. Using the model which represents a direct (or float) charge system implementation the performance sensitivity to the following parameter variations is reported: (1) solar roof slope angle; (2) ratio of the number of series cells in the solar array to the number of series cells in the lead-acid battery; and (3) battery size. For a Cleveland site location, a system with no on site energy storage and with a maximum power tracking inverter which feeds back excess power to the utility was shown to have 19 percent greater net system output than the second place system. The experiment test plan is described. The load control and data acquisition system and the data display panel for the residence are discussed

Diseño de una mano robótica para uso docente

El trabajo que se desarrolla a continuación es para uso docente, en el cual se presenta el diseño y la construcción de una mano robótica sencilla de tres dedos antropomórficos. El objetivo del presente trabajo es el de obtener un primer prototipo de este manipulador robótico sencillo y de bajo coste para que los alumnos aprendan a programar dicho dispositivo de una forma sencilla mediante Simulink. Otro de los propósitos es enseñar al alumno que mediante sencillos métodos de fabricación se pueden diseñar dispositivos funcionales, capaces de emular alguno de los movimientos de la mano humana, sin necesidad de utilizar tecnologías complejas. La mano robótica que se ha construido consta de tres dedos antropomórficos, cada uno de los cuales está constituido de tres falanges, cuyos movimientos están acoplados mediante un sistema mecánico rígido de transmisión. El movimiento de cada uno de los dedos se controla a través de dos tendones en configuración agonista-antagonista conectados a un servomotor. Los dedos del manipulador robótico están pensados y diseñados con medidas reales y formas similares a los de la mano humana, para así conseguir movimientos verosímiles a los de una mano real. El diseño, tanto de los dedos como de la palma de la mano y del resto de componentes mecánicos que conforman el diseño final se ha realizado mediante el software Solidworks. La fabricación de cada parte del dedo, palma de la mano, soportes varios se han realizado mediante la impresión 3D. El principal objetivo de utilizar este método de fabricación ha sido disminuir los costes para el desarrollo del prototipo, ya que para su uso docente se necesitan varias unidades. Para concluir se puede decir que este diseño presenta una alternativa de bajo coste y permite la actuación y control de una mano artificial con un número pequeño de grados de libertad.The work being done below is for teaching purposes, in which the design and construction of a simple three anthropomorphic robotic hand fingers is presented. The aim of this study is to obtain a first prototype of this robot manipulator (simple and low cost) for students to learn how to program the device in a simple way by Simulink. Another purpose is to teach them that by simple manufacturing methods, they can design functional devices, capable of emulating any of the movements of the human hand, without the use of complex technologies. The robot hand has been constructed with three anthropomorphic fingers; each one consists of three phalanges, whose movements are mechanically coupled by a rigid drive system. The movement of each finger is controlled by two tendons in agonistantagonist configuration connected to a servomotor. The fingers of the robotic manipulator are conceived and designed with real measures and similar to those of the human hand, so it could be possible to get real hand movements. The design of both, the fingers and the palm of the hand, and the other mechanical components that make up the final design was performed using the Solidworks software. The manufacture of each of the finger, palm, and various supports was performed using 3D printing. The main objective of using this method of manufacture has been to reduce prototype’s costs. In conclusion it can be said that this design is a low cost alternative and allows actuation and control in an artificial hand with a small number of degrees of freedom.Ingeniería Electrónica Industrial y Automátic

RHINO: reconfigurable hardware interface for computation and radio

Field-programmable gate arrays, or FPGAs, provide an attractive computing platform for software-defined radio applications. Their reconfigurable nature allows many digital signal processing (DSP) algorithms to be highly parallelised within the FPGA fabric, while their customisable I/O interfaces allow simple interfacing to analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs). However, FPGA boards that deliver sufficient performance to be useful in real-world applications are generally expensive. Rhino is an FPGA-based hardware processing platform that primarily supports software-defined radio applications. The final cost estimate for a complete Rhino system is under $1700, cheaper than similar FPGA boards that deliver much lower performance

Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one

A compact high-energy particle detector for low-cost deep space missions

Over the last few decades particle physics has led to many new discoveries, laying the foundation for modern science. However, there are still many unanswered questions which the next generation of particle detectors could address, potentially expanding our knowledge and understanding of the Universe. Owing to recent technological advancements, electronic sensors are now able to acquire measurements previously unobtainable, creating opportunities for new deep-space high-energy particle missions. Consequently, a new compact instrument was developed capable of detecting gamma rays, neutrons and charged particles. This instrument combines the latest in FPGA System-on-Chip technology as the central processor and a 3x3 array of silicon photomultipliers coupled with an organic plastic scintillator as the detector. Using modern digital pulse shape discrimination and signal processing techniques, the scintillator and photomultiplier combination has been shown to accurately discriminate between the di_erent particle types and provide information such as total energy and incident direction. The instrument demonstrated the ability to capture 30,000 particle events per second across 9 channels - around 15 times that of the U.S. based CLAS detector. Furthermore, the input signals are simultaneously sampled at a maximum rate of 5 GSPS across all channels with 14-bit resolution. Future developments will include FPGA-implemented digital signal processing as well as hardware design for small satellite based deep-space missions that can overcome radiation vulnerability

A Ringamp-Assisted, Output Capacitor-less Analog CMOS Low-Dropout Voltage Regulator

Continued advancements in state-of-the-art integrated circuits have furthered trends toward higher computational performance and increased functionality within smaller circuit area footprints, all while improving power efficiencies to meet the demands of mobile and battery-powered applications. A significant portion of these advancements have been enabled by continued scaling of CMOS technology into smaller process node sizes, facilitating faster digital systems and power optimized computation. However, this scaling has degraded classic analog amplifying circuit structures with reduced voltage headroom and lower device output resistance; and thus, lower available intrinsic gain. This work investigates these trends and their impact for fine-grain Low-Dropout (LDO) Voltage Regulators, leading to a presented design methodology and implementation of a state-of-the-art Ringamp-Assisted, Output Capacitor-less Analog CMOS LDO Voltage Regulator capable of both power scaling and process node scaling for general SoC applications

A PCI Express board designed to interface with the electronic phase-2 upgrades of the ATLAS detectors at CERN

Nei prossimi 10 anni è in previsione un aggiornamento radicale dell'acceleratore LHC al CERN finalizzato al raggiungimento di più alti valori di luminosità istantanea (oltre \begin{math}5 \times 10^{34}cm^{-2}s^{-1}\end{math}) ed integrata (oltre un fattore 10 rispetto a quella attuale). Conseguentemente, anche i rilevatori degli esperimenti che lavorano al CERN, così come i loro sistemi di acquisizione dati, dovranno essere aggiornati per poter gestire un flusso notevolmente maggiore rispetto a quello utilizzato finora. Questa tesi tratta in particolare di una nuova scheda elettronica di lettura, progettata e testata nel laboratorio di elettronica del Dipartimento di Fisica ed Astronomia dell'Università di Bologna e nel laboratorio di elettronica della Sezione INFN (Istituto Nazionale di Fisica Nucleare) di Bologna. Le motivazioni che hanno indotto lo sviluppo della scheda prototipale sono molteplici. Un primo obiettivo da perseguire è stato quello di aggiornare la versione attuale delle schede elettroniche di acquisizione dati usate oggi nel Pixel Detector dell'esperimento ATLAS, visto che sono anch'esse sotto la responsabilità della sezione INFN di Bologna. Secondariamente, la scheda (nominata Pixel-ROD) è orientata a gestire le esigenze elettroniche che seguiranno l'upgrade di LHC durante la fase 2. La complessità del progetto e l'inerzia intrinseca di una vasta collaborazione come quella di ATLAS, hanno poi indotto lo sviluppo di questo progetto elettronico in largo anticipo rispetto al vero upgrade di fase 2 di LHC, previsto per il 2024. In questo modo saranno anche più facilmente eseguibili eventuali aggiornamenti tecnologici in corso d'opera, senza dover riprogettare da zero un sistema di acquisizione dati completo