Ring Amplifier Optimized for High Resolution Analog-to-Digital Converter Applications

In recent years, SAR ADCs have been shown to acheive faster conversion times and improved power efficiencies due to their simple building blocks that are digital in nature and scale favorably with technology. High resolution ADCs with stringent noise requirement has led to the adoption of hybrid ADC architectures such as the two-step SAR. The two-step SAR ADC, also known as pipelined SAR ADC, combine the concepts of SAR and Pipeline ADC architecture where a residue amplifier provides a critical amplification step. An amplifier architecture well suited for residue amplification known as Ring Amplifier (RAMP) has enabled power efficient two-step SAR ADCs. However, RAMP based ADCs with greater than 14 bits of resolution has not been attempted in previous literature. In this work, the design and measurement of a high-resolution two-step SAR ADC utilizing an enhanced RAMP is demonstrated. Additional circuit techniques are introduced that contribute to the energy-efficiency of the ADC. The ADC implemented in 0.18$\mu$m technology achieves a DR of 95dB and a Schreier FOM better than 180dB at both 2MS/s and 15MS/s

Design of Inverter Based CMOS Amplifiers in Deep Nanoscale Technologies

In this work, it is proposed a fully differential ring amplifier topology with a deadzone voltage created by a CMOS resistor with a biasing circuit to increase the robustness over PVT variations. The study focuses on analyzing the performance of the ring amplifier over process, temperature, and supply voltage variations, in order to guarantee a viable industrial employment in a 7 nm FinFET CMOS technology node for being used as residue amplifier in ADCs. A ring amplifier is a small modular amplifier, derived from a ring oscillator. It is simple enough that it can quickly be designed using only a few inverters, capacitors, and switches. It can amplify with rail-to-rail output swing, competently charge large capacitive loads using slew-based charging, and scale well in performance according to process trends. In typical process corner, a gain of 72 dB is achieved with a settling time of 150 ps. Throughout the study, the proposed topology is compared with others presented in literature showing better results over corners and presenting a faster response. The proposed topology isn’t yet suitable for industry use, because it presents one corner significantly slower than the rest, namely process corner FF 125 °C, and process corner FS -40 °C with a small oscillation throughout the entire amplification period. Nevertheless, it proved itself to be a promising technique, showing a high gain and a fast settling without oscillation phase, with room for improvement.Neste trabalho, é proposta uma topologia de ring amplifier com a deadzone a ser criada através de uma resistência CMOS com um circuito de polarização para aumentar a robustez para as variações PVT. O estudo foca-se em analisar a performance do ring amplifier nas variações de processo, temperatura e tensão de alimentação, de forma a garantir um uso viável em indústria na tecnologia de 7 nm FinFET CMOS, para ser usado como amplificador de resíduo em ADCs. Um ring amplifier é um pequeno amplificador modular, derivado do ring oscillator. É simples o suficiente para ser facilmente projetado usando apenas poucos inversores, condensadores e interruptores. Consegue amplificar com rail-to-rail output swing, carregar grandes cargas capacitivas com carregamento slew-based e escalar bem em termos de performance de acordo com o processo. No typical process corner, foi obtido um ganho de 72 dB com um tempo de estabilização de 150 ps. Durante o estudo, a topologia proposta é comparada com outras presentes na literatura mostrando melhores resultados over corners e apresentando uma resposta mais rápida. A topologia proposta ainda não está preparada para uso industrial uma vez que apresenta um corner significativamente mais lento que os restantes, nomeadamente, process corner FF 125 °C, e outro process corner, FS -40 °C, com uma pequena oscilação durante todo o período de amplificação. Todavia, provou ser uma técnica promissora, apresentando um ganho elevado e uma rápida estabilização sem fase de oscilação, com espaço para melhoria

Spatial modulation schemes and modem architectures for millimeter wave radio systems

The rapid growth of wireless industry opens the door to several use cases such as internet of things and device-to-device communications, which require boosting the reliability and the spectral efficiency of the wireless access network, while reducing the energy consumption at the terminals. The vast spectrum available in millimeter-wave (mmWave) frequency band is one of the most promising candidates to achieve high-speed communications. However, the propagation of the radio signals at high carrier frequencies suffers from severe path-loss which reduces the coverage area. Fortunately, the small wavelengths of the mmWave signals allow packing a large number of antennas not only at the base station (BS) but also at the user terminal (UT). These massive antenna arrays can be exploited to attain high beamforming and combining gains and overcome the path-loss associated with the mmWave propagation. In conventional (fully digital) multiple-input-multiple-output (MIMO) transceivers, each antenna is connected to a specific radio-frequency (RF) chain and high resolution analog-to-digital-converter. Unfortunately, these devices are expensive and power hungry especially at mmWave frequency band and when operating in large bandwidths. Having this in mind, several MIMO transceiver architectures have been proposed with the purpose of reducing the hardware cost and the energy consumption. Fully connected hybrid analog and digital precoding schemes were proposed in with the aim of replacing some of the conventional RF chains by energy efficient analog devices. These fully connected mapping requires many analog devices that leads to non-negligible energy consumption. Partially connected hybrid architectures have been proposed to improve the energy efficiency of the fully connected transceivers by reducing the number of analog devices. Simplifying the transceiver’s architecture to reduce the power consumption results in a degradation of the attained spectral efficiency. In this PhD dissertation, we propose novel modulation schemes and massive MIMO transceiver design to combat the challenges at the mmWave cellular systems. The structure of the doctoral manuscript can be expressed as In Chapter 1, we introduce the transceiver design challenges at mmWave cellular communications. Then, we illustrate several state of the art architectures and highlight their limitations. After that, we propose scheme that attains high-energy efficiency and spectrum efficiency. In chapter 2, first, we mathematically describe the state of the art of the SM and highlight the main challenges with these schemes when applied at mmWave frequency band. In order to combat these challenges (for example, high cost and high power consumption), we propose novel SM schemes specifically designed for mmWave massive MIMO systems. After that, we explain how these schemes can be exploited in attaining energy efficient UT architecture. Finally, we present the channel model, systems assumptions and the transceiver devices power consumption models. In chapter 3, we consider single user SM system. First, we propose downlink (DL) receive SM (RSM) scheme where the UT can be implemented with single or multiple radio-frequency chains and the BS can be fully digital or hybrid architecture. Moreover, we consider different precoders at the BS and propose low complexity and efficient antenna selection schemes for narrowband and wideband transmissions. After that, we propose joint uplink-downlink SM scheme where we consider RSM in the DL and transmit SM (TSM) in the UL based on energy efficient hybrid UT architecture. In chapter 4, we extend the SM system to the multi-user case. Specifically, we develop joint multi-user power allocation, user selection and antenna selection algorithms for the broadcast and the multiple access channels. Chapter 5 is presented for concluding the thesis and proposing future research directions.Considerando los altos requerimientos de los servicios de nueva generación, las infraestructuras de red actual se han visto obligadas a evolucionar en la forma de manejar los diferentes recursos de red y computación. Con este fin, nuevas tecnologías han surgido para soportar las funcionalidades necesarias para esta evolución, significando también un gran cambio de paradigma en el diseño de arquitecturas para la futura implementación de redes.En este sentido, este documento de tesis doctoral presenta un análisis sobre estas tecnologías, enfocado en el caso de redes inter/intra Data Centre. Por consiguiente, la introducción de tecnologías basadas en redes ópticas ha sido estudiada, con el fin de identificar problemas actuales que puedan llegar a ser solucionados mediante el diseño y aplicación de nuevas técnicas, asimismo como a través del desarrollo o la extensión de los componentes de arquitectura de red.Con este propósito, se han definido una serie de propuestas relacionadas con aspectos cruciales, así como el control de dispositivos ópticos por SDN para habilitar el manejo de redes híbridas, la necesidad de definir un mecanismo de descubrimiento de topologías ópticas capaz de exponer información precisa, y el analizar las brechas existentes para la definición de una arquitectura común en fin de soportar las comunicaciones 5G.Para validar estas propuestas, se han presentado una serie de validaciones experimentales por medio de escenarios de prueba específicos, demostrando los avances en control, orquestación, virtualización y manejo de recursos con el fin de optimizar su utilización. Los resultados expuestos, además de corroborar la correcta operación de los métodos y componentes propuestos, abre el camino hacia nuevas formas de adaptar los actuales despliegues de red respecto a los desafíos definidos en el inicio de una nueva era de las telecomunicaciones.Postprint (published version