25,408 research outputs found
Verification of Sequential Circuits by Tests-As-Proofs Paradigm
We introduce an algorithm for detection of bugs in sequential circuits. This
algorithm is incomplete i.e. its failure to find a bug breaking a property P
does not imply that P holds. The appeal of incomplete algorithms is that they
scale better than their complete counterparts. However, to make an incomplete
algorithm effective one needs to guarantee that the probability of finding a
bug is reasonably high. We try to achieve such effectiveness by employing the
Test-As-Proofs (TAP) paradigm. In our TAP based approach, a counterexample is
built as a sequence of states extracted from proofs that some local variations
of property P hold. This increases the probability that a) a representative set
of states is examined and that b) the considered states are relevant to
property P.
We describe an algorithm of test generation based on the TAP paradigm and
give preliminary experimental results
Parallelization of cycle-based logic simulation
Verification of digital circuits by Cycle-based simulation can be performed in parallel. The parallel implementation requires two phases: the compilation phase, that sets up the data needed for the
execution of the simulation, and the simulation phase, that consists in executing the parallel simulation of the considered circuit for a certain number of cycles. During the early phase of design, compilation phase has to be repeated each time a bug is found. Thus, if the time of the compilation phase is too high, the advantages stemming from the parallel approach may be lost. In this work we propose an
effective version of the compilation phase and compute the corresponding execution time. We also analyze the percentage of execution time required by the different steps of the compilation phase for
a set of literature benchmarks. Further, we implemented the simulation phase exploiting the GPU architecture, and we computed the execution times for a set of benchmarks obtaining values comparable
with literature ones. Finally, we implemented the sequential version of the Cycle-based simulation in such a way that the execution time is optimized. We used the sequential values to compute the speedup
of the parallel version for the considered set of benchmarks
Hybrid computer Monte-Carlo techniques
Hybrid analog-digital computer systems for Monte Carlo method application
On applying the set covering model to reseeding
The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the tradeoff between area overhead and global test length as well as to deal with larger circuits
Bridging the Testing Speed Gap: Design for Delay Testability
The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addresse
- …