New mathematical formulation for designing a fully differential self-biased folded cascode amplifier

One of the most important building blocks in analog circuit design is the operational amplifiers. This is because of their versatility and wide spread usage in many applications such as communications transmitters and receivers, analog to digital converters, or any other application that requires a small signal to be amplified. The basic amplifier topologies are introduced. Then, some operational amplifiers topologies are introduced with some techniques to self bias these amplifiers. The folded cascode fully differential Op-Amp with self bias is presented. This is one of the newest amplifier topologies which provide stable self-biased amplifiers. A new mathematical model for fully differential folded cascode amplifiers is presented and generalized to include the family of fully differential complementary amplifiers. This formulation focuses on deriving detailed design equations for the amplifier gain and frequency response. The equations are verified through time domain and frequency domain simulations of different fabrication processes to ensure the validity of the model across a wide range of processes. The model was verified against TMSC 180nm, 250nm, and 350nm fabrication processes. The new model agrees well with simulations; with 1% error for the amplifier gain and \u3c7% error for amplifier bandwidth. The relatively high error value for the bandwidth is because the model considers the worst case scenario and overestimates the output capacitance. Finally, the algorithm of getting this formulation is extended to include special and commonly used cases. This formulation proved to be very useful in designing stable, self-biased, fully differential folded cascode amplifiers

Amplifier performance enhancement methods using positive feedback techniques

The dramatic growth in the hi-tech sector of consumer market has created many unprecedented challenges in the area of integrated circuits. The present and future communication and entertainment systems including high speed cable and DSL modems, broadband wired and wireless systems, and high definition visual products require very fast and high accuracy amplifiers, data converters and filters. Analog design in the new digital CMOS submicron processes is becoming an economical necessity in the industry. The task of building fast Op-Amp with very high DC-gain is already a very difficult problem, and this task has become more difficult using these new submicron digital processes, where traditional gain enhancement techniques are loosing their ability to deliver amplifiers with sufficient gain. In this work three new methods of implementing the internal positive-feedback to build very high DC-gain amplifiers with very low gain sensitivity to signal swings are presented. Amplifiers proposed in the first method have very high current-controlled gain. A DC gain larger than 100dB is possible without limiting the speed of the amplifier. Amplifiers proposed in the second method exhibit both enhanced speed, i.e., unity gain frequency, and enhanced gain. Amplifiers proposed in the third method have self-adjusting gain without extra control block. An implementation of a 3 bit multiplying DAC in a 9-bit 165MS/s pipeline ADC built in a 1.8V, 0.21mu digital CMOS process using one of the proposed amplifiers is described. Test results show high gain with very fast settling

A 90 dB, 85 MHz operational transconductance amplifier (OTA) using gain boosting technique

Gain and speed are the two most important parameters of an amplifier. Optimizing an amplifier for both of these parameters leads to contradicting demands. Various architectures have been reported to obtain high gain from the circuits. Cascode circuits are widely used in circuit design at places where high gain and high output impedances are required. Different architectures like triple cascode topology, dynamic biasing and a positive feedback amplifier have been used to obtain high gains. These architectures have been compared in this thesis along with drawbacks and advantages of each

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (s) are the highest when compared to other reported FCOTAs in the literature

Slew-rate enhancement and trojan state avoiding for fully-differential operational amplifier

Operational amplifiers are fundamental building blocks in modern analog and mixed-signal systems such as data converters, switched-capacitor circuits, and filters. The fully-differential structure is extensively used in these applications because of its improved dynamic performance with respect to such aspects as signal-to-noise ratio (SNR) and total harmonic distortion (THD) when compared to its single-ended counterpart. In some of these applications, the fully-differential amplifier is required to have fast transient settling time without slew-rate limitations. Power consumption also must be taken into consideration because low power consumption can significantly reduce a battery\u27s weight and size, and extend its life-time. A Class A amplifier is a difficult configuration in which to conciliate all these requirements, since its fixed bias current can limit its maximum output current. To simultaneously meet both slew-rate and power consumption requirements, several slew-rate enhancement (SRE) techniques have been proposed in the literature, but all of them are either incompatible with the low voltage operation or exhibit either degradation in linearity or increase in circuit complexity. This thesis presents a simple SRE technique, efficient in both power and area usage, improve the slew rate while overcoming the drawbacks of state-of-the-art SRE techniques. In this work, several existing SRE techniques are discussed, and their advantages and disadvantages are identified. The proposed SRE technique is based on excess transient detection and feedback. A transient signal can be detected at the internal nodes of amplifier. Once the detected transient signal is found to be larger than a pre-defined turn-on value, the excess transient signal can be instantaneously amplified to turn on a dynamic current source and feed it back to the amplifier for current boosting. This pre-defined turn-on voltage results in a SRE circuit being solidly off during quiescent state. Small-signal performance and linearity of the original amplifier can be thus well preserved. Thanks to this excess transient feedback concept, the implementation is much simpler than that of previously reported methods, and the static power overhead is also very small. Using the proposed SRE method, a fully-differential folded-cascode two-stage op-amp has been designed and fabricated using IBM 130nm process. This amplifier is designed to validate the proposed method of improving an amplifier\u27s input-stage slew-rate. If the tail current doubles during slewing, the simulation result indicates that, at all corners, with temperature from 0°C to 60°C the average slew-rate can be enhanced by a factor of 2.6 and the 1% settling time after a large input step is reduced by 30% compared to the vales without using SRE. Any further increment in the tail transient current can further increase the internal slew rate and eventually make it equal to the output-stage slew-rate. It is well-known that self-stabilized circuits, such as current, voltage and frequency references, are vulnerable to a problem of multiple operating points; this is also known as the start-up problem. An op-amp can suffer from the same problem when performance enhancement feedback is being used. In particular, a slew rate enhancement circuit (SRE) can be used to provide performance enhancement in low-power high-speed op-amp design. For such circuits, a systematic method for detecting and removal of Trojan states is presented. Using a design example and simulation results, it is demonstrated that the proposed method can effectively remove a Trojan state in an op-amp without degrading the improved slew-rate

Analogue micropower FET techniques review

A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low-power applications is presented in this review. The topics discussed include sub-threshold operation in FET devices, micro-current mirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transconductance-capacitance and log-domain filters and strained-channel FET technologies

Design of Analog CMOS Circuits for Batteryless Implantable Telemetry Systems

A wireless biomedical telemetry system is a device that collects biomedical signal measurements and transmits data through wireless RF communication. Testing medical treatments often involves experimentation on small laboratory animals, such as genetically modified mice and rats. Using batteries as a power source results in many practical issues, such as increased size of the implant and limited operating lifetime. Wireless power harvesting for implantable biomedical devices removes the need for batteries integrated into the implant. This will reduce device size and remove the need for surgical replacement due to battery depletion. Resonant inductive coupling achieves wireless power transfer in a manner modelled by a step down transformer. With this methodology, power harvesting for an implantable device is realized with the use of a large primary coil external to the subject, and a smaller secondary coil integrated into the implant. The signal received from the secondary coil must be regulated to provide a stable direct current (DC) power supply, which will be used to power the electronics in the implantable device. The focus of this work is on development of an electronic front-end for wireless powering of an implantable biomedical device. The energy harvesting front-end circuit is comprised of a rectifier, LDO regulator, and a temperature insensitive voltage reference. Physical design of the front-end circuit is developed in 0.13um CMOS technology with careful attention to analog layout issues. Post-layout simulation results are presented for each sub-block as well as the full front-end structure. The LDO regulator operates with supply voltages in the range of 1V to 1.5V with quiescent current of 10.5uA The complete power receiver front-end has a power conversion efficiency of up to 29%

A digital background calibration technique for pipeline ADCs

http://www.worldcat.org/oclc/4258158

Design of an Active Harmonic Rejection N-Path Filter for Highly Tunable RF Channel Selection

As the number of wireless devices in the world increases, so does the demand for flexible radio receiver architectures capable of operating over a wide range of frequencies and communication protocols. The resonance-based channel-select filters used in traditional radio architectures have a fixed frequency response, making them poorly suited for such a receiver. The N-path filter is based on 1960s technology that has received renewed interest in recent years for its application as a linear high Q filter at radio frequencies. N-path filters use passive mixers to apply a frequency transformation to a baseband low-pass filter in order to achieve a high-Q band-pass response at high frequencies. The clock frequency determines the center frequency of the band-pass filter, which makes the filter highly tunable over a broad frequency range. Issues with harmonic transfer and poor attenuation limit the feasibility of using N-path filters in practice. The goal of this thesis is to design an integrated active N-path filter that improves upon the passive N-path filter’s poor harmonic rejection and limited outof- band attenuation. The integrated circuit (IC) is implemented using the CMRF8SF 130nm CMOS process. The design uses a multi-phase clock generation circuit to implement a harmonic rejection mixer in order to suppress the 3rd and 5th harmonic. The completed active N-path filter has a tuning range of 200MHz to 1GHz and the out-ofband attenuation exceeds 60dB throughout this range. The frequency response exhibits a 14.7dB gain at the center frequency and a -3dB bandwidth of 6.8MHz