A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable hardware can provide all these features. However the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfigurable resources while carrying out both prefetch and replacement techniques that cooperate to hide most of the reconfiguration delays. In our scheduling environment task-graphs are analyzed at design-time to extract useful information. This information is used at run-time to obtain near-optimal schedules, escaping from local-optimum decisions, while only carrying out simple computations. Moreover, we have developed a hardware implementation of the scheduler that applies all the optimization techniques while introducing a delay of only a few clock cycles. In the experiments our scheduler clearly outperforms conventional run-time schedulers based on As-Soon-As-Possible techniques. In addition, our replacement policy, specially designed for reconfigurable systems, achieves almost optimal results both regarding reuse and performance

Software tools for real-time simulation and control

The objective of this thesis is to design and simulate a multi-agent based energy management system for a shipboard power system in hard real-time environment. The automatic reconfiguration of shipboard power systems is essential to improve survivability. Multi-agent technology is used in designing the reconfigurable energy management system using a self-stabilizing maximum flow algorithm. The agent based energy management system is designed in a Matlab/Simulink environment. Reconfiguration is performed for several situations including start-up, loss of an agent, limited available power, and distribution to priority ranked loads. The number of steps taken to reach the global solution and the time taken are very promising. With the growing importance of timing accuracy in simulating control systems during design and development, there is an increased need for these simulations to run in a real-time environment. This research further focuses on software tools that support hard real-time environment to run real-time simulations. A detailed survey has been conducted on freely available real-time operating systems and other software tools to setup a desktop PC supporting real-time environment. Matlab/Simulink/RTW-RTAI was selected as real-time computer aided control design software for demonstrating real-time simulation of agent based energy management system. The timing accuracy of these simulations has been verified successfully

Self-tuning run-time reconfigurable PID controller

Digital PID control algorithm is one of the most commonly used algorithms in the control systems area. This algorithm is very well known, it is simple, easily implementable in the computer control systems and most of all its operation is very predictable. Thus PID control has got well known impact on the control system behavior. However, in its simple form the controller have no reconfiguration support. In a case of the controlled system substantial changes (or the whole control environment, in the wider aspect, for example if the disturbances characteristics would change) it is not possible to make the PID controller robust enough. In this paper a new structure of digital PID controller is proposed, where the policy-based computing is used to equip the controller with the ability to adjust it's behavior according to the environmental changes. Application to the electro-oil evaporator which is a part of distillation installation is used to show the new controller structure in operation

Adaptive Wireless Networking

This paper presents the Adaptive Wireless Networking (AWGN) project. The project aims to develop methods and technologies that can be used to design efficient adaptable and reconfigurable mobile terminals for future wireless communication systems. An overview of the activities in the project is given. Furthermore our vision on adaptivity in wireless communications and suggestions for future activities are presented

Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized

The Chameleon Architecture for Streaming DSP Applications

We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool

Reconfigurable Mobile Multimedia Systems

This paper discusses reconfigurability issues in lowpower hand-held multimedia systems, with particular emphasis on energy conservation. We claim that a radical new approach has to be taken in order to fulfill the requirements - in terms of processing power and energy consumption - of future mobile applications. A reconfigurable systems-architecture in combination with a QoS driven operating system is introduced that can deal with the inherent dynamics of a mobile system. We present the preliminary results of studies we have done on reconfiguration in hand-held mobile computers: by having reconfigurable media streams, by using reconfigurable processing modules and by migrating functions