Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input

In low power current mode signal processing circuits it is often necessary to use current mirrors to replicate and amplify/attenuate current signals and clamp the voltage of nodes with high parasitic capacitances so that the smallest currents do not introduce unacceptable delays. The use of tunable active-input current mirrors would meet both requirements. In conventional active-input current mirrors, stability compensation is required. Furthermore, once stabilized, the input current cannot be made arbitrarily small. In this paper we introduce two new active-input current mirrors that clamp their input node to a given voltage. One of them does not require compensation, while the other may under some circumstances. However, for both, the input current may take any value. The mirrors can operate with their transistors biased in strong inversion, weak inversion, or even as CMOS compatible lateral bipolar devices. If it is biased in weak inversion or as lateral bipolars, the current mirror gain can be tuned over a very wide range. According to the experimental measurements provided in this paper, the input current may spawn beyond nine decades and the current mirror gain can be tuned over 11 decades. As an application example, a sinusoidal gm-C-based VCO has been fabricated, whose oscillation frequency could be tuned for over seven decades, between 74 mHz and 1 MHz.Office of Naval Research (USA) N00014-95-1-040

CMOS output buffer wave shaper

As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication

Simulations of pulse signals with X-parameters

Nonlinearity is becoming increasingly important to IC technologies. From the PHD formalism, X-parameter models provide an accurate frequency-domain method under large-signal operating points to characterize their nonlinear behaviors. In this work, X-parameter models are investigated to handle time-domain pulse signals which is critical to IC signal integrity but was not studied before. Two representative circuits, an analog LNA and a digital CMOS buffer, were employed to characterize the X-parameter performance. The results obtained in this paper provide the first hand data for pulse signal responses of X-parameters in signal integrity modelings. © 2011 IEEE.published_or_final_versionThe IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS 2011), San Jose, CA., 23-26 October 2011. In Proceedings of the IEEE 20th EPEPS, 2011, p. 129-13

Low Voltage CMOS SAR ADC Design

This project centers on the design of a single ended 10-bit successive approximation register analog to digital converter (SAR ADC for short) that easily interfaces to a micro-controller, such as an Arduino. With micro-controller interfacing in mind, the universal data transfer technique of SPI proved an easy way to communicate between the ADC and the micro-controller. The ADC has a range of 1V (highest code value) to 0V (lowest code value) and operates from a single voltage rail value of 1.8V. Typical SPI clock speeds run on the order of 2MHz and with a 10-bit ADC this means a sampling speed of 200k samples per second, though the design could run at faster speeds. While this design does not provide groundbreaking circuit designs or ideas, it does provide an in-depth learning experience for sub-micron (180nm) circuit design

Small Form Factor Hybrid CMOS/GaN Buck Converters for 10W Point of Load Applications

abstract: Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing. This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor. Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.Dissertation/ThesisMasters Thesis Electrical Engineering 201

A Zero Bias Pixel Sensor and its Zero-Bias Column Buffer-Direct-Injection Circuit

Two pixel sensors, namely active pixel sensor (APS) and pseudo-active pixel sensor (PAPS), are reviewed to show that APS suffers from dark current while PAPS suffers from leakage current. Then a new pixel sensor called  zero bias pixel sensor (ZBPS) in which only two MOS switches in addition to the photodiode are used, one for connecting the pixel’s photodiode to a column bus and the other for bypassing it. A zero-bias column buffer-direct-injection (ZCBDI) circuit, which is similar to a regulated cascode amplifier, is used to control the voltage at column bus at zero. All ZBPS pixels are guaranteed to work at zero voltage at all times to eliminate the dark current as well as leakage current. A case of a 10 µm x 10 µm ZBPS pixel designed with standard 0.18 µm CMOS process is studied through simulation. This pixel generates a photocurrent within a range from 1 pA to 100 nA. To handle a large variation of photocurrent while maintaining zero column voltage, the ZCBDI is designed using differential cascode, common source, and buffer stages and then compensated for 50 degree phase margin. Transient simulation shows that the pixel steady state response time is around 1.406 ms, leading to at most 5.5 frames per second for an image of 128 x 128 ZBPS pixels. The fill factor of ZBPS for this case is around 59%

A 10-bit 4 MS/s SAR ADC with Fully-Dynamic Duty-Cycled Input Driver

This paper presents a duty-cycled input driver for a SAR ADC. Being a discrete-time system, the SAR ADC requires an accurate input signal only at its sampling moment. This motivates the use of a duty-cycled input driver which can be turned off during the conversion phase to save power. In this way, the power consumption of the SAR ADC together with its input driver becomes fully dynamic. This idea is applied to a 10-bit 4 MS/s SAR ADC with unity-gain input drivers. Fabricated in 65 nm CMOS, the prototype achieves 8.9 ENOB and 69.9 dB SFDR while consuming 35.0 µW. This leads to a Walden FoM of 18.3 fJ/conversion-step for the ADC including driver.</p