Dynamic selection and estimation of the digital predistorter parameters for power amplifier linearization

© © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a new technique that dynamically estimates and updates the coefficients of a digital predistorter (DPD) for power amplifier (PA) linearization. The proposed technique is dynamic in the sense of estimating, at every iteration of the coefficient's update, only the minimum necessary parameters according to a criterion based on the residual estimation error. At the first step, the original basis functions defining the DPD in the forward path are orthonormalized for DPD adaptation in the feedback path by means of a precalculated principal component analysis (PCA) transformation. The robustness and reliability of the precalculated PCA transformation (i.e., PCA transformation matrix obtained off line and only once) is tested and verified. Then, at the second step, a properly modified partial least squares (PLS) method, named dynamic partial least squares (DPLS), is applied to obtain the minimum and most relevant transformed components required for updating the coefficients of the DPD linearizer. The combination of the PCA transformation with the DPLS extraction of components is equivalent to a canonical correlation analysis (CCA) updating solution, which is optimum in the sense of generating components with maximum correlation (instead of maximum covariance as in the case of the DPLS extraction alone). The proposed dynamic extraction technique is evaluated and compared in terms of computational cost and performance with the commonly used QR decomposition approach for solving the least squares (LS) problem. Experimental results show that the proposed method (i.e., combining PCA with DPLS) drastically reduces the amount of DPD coefficients to be estimated while maintaining the same linearization performance.Peer ReviewedPostprint (author's final draft

A fast engineering approach to high efficiency power amplifier linearization for avionics applications

This PhD thesis provides a fast engineering approach to the design of digital predistortion (DPD) linearizers from several perspectives: i) enhancing the off-line training performance of open-loop DPD, ii) providing robustness and reducing the computational complexity of the parameters identification subsystem and, iii) importing machine learning techniques to favor the automatic tuning of power amplifiers (PAs) and DPD linearizers with several free-parameters to maximize power efficiency while meeting the linearity specifications. One of the essential parts of unmanned aerial vehicles (UAV) is the avionics, being the radio control one of the earliest avionics present in the UAV. Unlike the control signal, for transferring user data (such as images, video, etc.) real-time from the drone to the ground station, large transmission rates are required. The PA is a key element in the transmitter chain to guarantee the data transmission (video, photo, etc.) over a long range from the ground station. The more linear output power, the better the coverage or alternatively, with the same coverage, better SNR allows the use of high-order modulation schemes and thus higher transmission rates are achieved. In the context of UAV wireless communications, the power consumption, size and weight of the payload is of significant importance. Therefore, the PA design has to take into account the compromise among bandwidth, output power, linearity and power efficiency (very critical in battery-supplied devices). The PA can be designed to maximize its power efficiency or its linearity, but not both. Therefore, a way to deal with this inherent trade-off is to design high efficient amplification topologies and let the PA linearizers take care of the linearity requirements. Among the linearizers, DPD linearization is the preferred solution to both academia and industry, for its high flexibility and linearization performance. In order to save as many computational and power resources as possible, the implementation of an open-loop DPD results a very attractive solution for UAV applications. This thesis contributes to the PA linearization, especially on off-line training for open-loop DPD, by presenting two different methods for reducing the design and operating costs of an open-loop DPD, based on the analysis of the DPD function. The first method focuses on the input domain analysis, proposing mesh-selecting (MeS) methods to accurately select the proper samples for a computationally efficient DPD parameter estimation. Focusing in the MeS method with better performance, the memory I-Q MeS method is combined with feature extraction dimensionality reduction technique to allow a computational complexity reduction in the identification subsystem by a factor of 65, in comparison to using the classical QR-LS solver and consecutive samples selection. In addition, the memory I-Q MeS method has been proved to be of crucial interest when training artificial neural networks (ANN) for DPD purposes, by significantly reducing the ANN training time. The second method involves the use of machine learning techniques in the DPD design procedure to enlarge the capacity of the DPD algorithm when considering a high number of free parameters to tune. On the one hand, the adaLIPO global optimization algorithm is used to find the best parameter configuration of a generalized memory polynomial behavioral model for DPD. On the other hand, a methodology to conduct a global optimization search is proposed to find the optimum values of a set of key circuit and system level parameters, that properly combined with DPD linearization and crest factor reduction techniques, can exploit at best dual-input PAs in terms of maximizing power efficiency along wide bandwidths while being compliant with the linearity specifications. The advantages of these proposed techniques have been validated through experimental tests and the obtained results are analyzed and discussed along this thesis.Aquesta tesi doctoral proporciona unes pautes per al disseny de linealitzadors basats en predistorsió digital (DPD) des de diverses perspectives: i) millorar el rendiment del DPD en llaç obert, ii) proporcionar robustesa i reduir la complexitat computacional del subsistema d'identificació de paràmetres i, iii) incorporació de tècniques d'aprenentatge automàtic per afavorir l'auto-ajustament d'amplificadors de potència (PAs) i linealitzadors DPD amb diversos graus de llibertat per poder maximitzar l’eficiència energètica i al mateix temps acomplir amb les especificacions de linealitat. Una de les parts essencials dels vehicles aeris no tripulats (UAV) _es l’aviònica, sent el radiocontrol un dels primers sistemes presents als UAV. Per transferir dades d'usuari (com ara imatges, vídeo, etc.) en temps real des del dron a l’estació terrestre, es requereixen taxes de transmissió grans. El PA _es un element clau de la cadena del transmissor per poder garantir la transmissió de dades a grans distàncies de l’estació terrestre. A major potència de sortida, més cobertura o, alternativament, amb la mateixa cobertura, millor relació senyal-soroll (SNR) la qual cosa permet l’ús d'esquemes de modulació d'ordres superiors i, per tant, aconseguir velocitats de transmissió més altes. En el context de les comunicacions sense fils en UAVs, el consum de potència, la mida i el pes de la càrrega útil són de vital importància. Per tant, el disseny del PA ha de tenir en compte el compromís entre ample de banda, potència de sortida, linealitat i eficiència energètica (molt crític en dispositius alimentats amb bateries). El PA es pot dissenyar per maximitzar la seva eficiència energètica o la seva linealitat, però no totes dues. Per tant, per afrontar aquest compromís s'utilitzen topologies amplificadores d'alta eficiència i es deixa que el linealitzador s'encarregui de garantir els nivells necessaris de linealitat. Entre els linealitzadors, la linealització DPD és la solució preferida tant per al món acadèmic com per a la indústria, per la seva alta flexibilitat i rendiment. Per tal d'estalviar tant recursos computacionals com consum de potència, la implementació d'un DPD en lla_c obert resulta una solució molt atractiva per a les aplicacions UAV. Aquesta tesi contribueix a la linealització del PA, especialment a l'entrenament fora de línia de linealitzadors DPD en llaç obert, presentant dos mètodes diferents per reduir el cost computacional i augmentar la fiabilitat dels DPDs en llaç obert. El primer mètode se centra en l’anàlisi de l’estadística del senyal d'entrada, proposant mètodes de selecció de malla (MeS) per seleccionar les mostres més significatives per a una estimació computacionalment eficient dels paràmetres del DPD. El mètode proposat IQ MeS amb memòria es pot combinar amb tècniques de reducció del model del DPD i d'aquesta manera poder aconseguir una reducció de la complexitat computacional en el subsistema d’identificació per un factor de 65, en comparació amb l’ús de l'algoritme clàssic QR-LS i selecció de mostres d'entrenament consecutives. El segon mètode consisteix en l’ús de tècniques d'aprenentatge automàtic pel disseny del DPD quan es considera un gran nombre de graus de llibertat (paràmetres) per sintonitzar. D'una banda, l'algorisme d’optimització global adaLIPO s'utilitza per trobar la millor configuració de paràmetres d'un model polinomial amb memòria generalitzat per a DPD. D'altra banda, es proposa una estratègia per l’optimització global d'un conjunt de paràmetres clau per al disseny a nivell de circuit i sistema, que combinats amb linealització DPD i les tècniques de reducció del factor de cresta, poden maximitzar l’eficiència de PAs d'entrada dual de gran ample de banda, alhora que compleixen les especificacions de linealitat. Els avantatges d'aquestes tècniques proposades s'han validat mitjançant proves experimentals i els resultats obtinguts s'analitzen i es discuteixen al llarg d'aquesta tesi

Auxiliary-Path-Assisted Digital Linearization of Wideband Wireless Receivers

Wireless communication systems in recent years have aimed at increasing data rates by ensuring flexible and efficient use of the radio spectrum. The dernier cri in this field has been in the area of carrier aggregation and cognitive radio. Carrier aggregation is a major component of LTE-Advanced. With carrier aggregation, a number of separate LTE carriers can be combined, by mobile network operators, to increase peak data rates and overall network capacity. Cognitive radios, on the other hand, allow efficient spectrum usage by locating and using spatially vacant spectral bands. High monolithic integration in these application fields can be achieved by employing receiver architectures such as the wideband direct conversion receiver topology. This is advantageous from the view point of cost, power consumption and size. However, many challenges exist, of particular importance is nonlinear distortion arising from analog front-end components such as low noise amplifiers (LNA). Nonlinear distortions especially become severe when several signals of varying amplitudes are received simultaneously. In such cases, nonlinear distortions stemming from strong signals may deteriorate the reception of the weaker signals, and also impair the receiver’s spectrum sensing capabilities. Nonlinearity, usually a consequence of dynamic range limitation, degrades performance in wideband multi-operator communications systems, and it will have a notable role in future wireless communication system design. This thesis presents a digital domain linearization technique that employs a very nonlinear auxiliary receiver path for nonlinear distortion cancellation. The proposed linearization technique relies on one-time adaptively-determined linearization coefficients for cancelling nonlinear distortions. Specifically, we take a look at canceling the troublesome in-band third order intermodulation products using the proposed technique. The proposed technique can be extended to cancel out both even and higher order odd intermodulation products. Dynamic behavioral models are used to account for RF nonlinearities, including memory effects which cannot be ignored in the wideband scenario. Since the proposed linearization technique involves the use of two receiver paths, techniques for correcting phase delays between the two paths are also introduced. Simplicity is the hallmark of the proposed linearization technique. It can achieve up to +30 dBm in IIP3 performance with ADC resolution being a major performance bottleneck. It also shows strong tolerance to strong blocker nonlinearities

Auxiliary-Path-Assisted Digital Linearization of Wideband Wireless Receivers

Wireless communication systems in recent years have aimed at increasing data rates by ensuring flexible and efficient use of the radio spectrum. The dernier cri in this field has been in the area of carrier aggregation and cognitive radio. Carrier aggregation is a major component of LTE-Advanced. With carrier aggregation, a number of separate LTE carriers can be combined, by mobile network operators, to increase peak data rates and overall network capacity. Cognitive radios, on the other hand, allow efficient spectrum usage by locating and using spatially vacant spectral bands. High monolithic integration in these application fields can be achieved by employing receiver architectures such as the wideband direct conversion receiver topology. This is advantageous from the view point of cost, power consumption and size. However, many challenges exist, of particular importance is nonlinear distortion arising from analog front-end components such as low noise amplifiers (LNA). Nonlinear distortions especially become severe when several signals of varying amplitudes are received simultaneously. In such cases, nonlinear distortions stemming from strong signals may deteriorate the reception of the weaker signals, and also impair the receiver’s spectrum sensing capabilities. Nonlinearity, usually a consequence of dynamic range limitation, degrades performance in wideband multi-operator communications systems, and it will have a notable role in future wireless communication system design. This thesis presents a digital domain linearization technique that employs a very nonlinear auxiliary receiver path for nonlinear distortion cancellation. The proposed linearization technique relies on one-time adaptively-determined linearization coefficients for cancelling nonlinear distortions. Specifically, we take a look at canceling the troublesome in-band third order intermodulation products using the proposed technique. The proposed technique can be extended to cancel out both even and higher order odd intermodulation products. Dynamic behavioral models are used to account for RF nonlinearities, including memory effects which cannot be ignored in the wideband scenario. Since the proposed linearization technique involves the use of two receiver paths, techniques for correcting phase delays between the two paths are also introduced. Simplicity is the hallmark of the proposed linearization technique. It can achieve up to +30 dBm in IIP3 performance with ADC resolution being a major performance bottleneck. It also shows strong tolerance to strong blocker nonlinearities

REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms