Solder Paste Scooping Detection by Multilevel Visual Inspection of Printed Circuit Boards

In this paper we introduce an automated Bayesian visual inspection framework for Printed Circuit Board (PCB) assemblies, which is able to simultaneously deal with various shaped Circuit Elements (CE) on multiple scales. We propose a novel Hierarchical Multi Marked Point Process (HMMPP) model for this purpose, and demonstrate its efficiency on the task of solder paste scooping detection and scoop area estimation, which are important factors regarding the strength of the joints. A global optimization process attempts to find the optimal configuration of circuit entities, considering the observed image data, prior knowledge, and interactions between the neighboring CEs. The computational requirements are kept tractable by a data driven stochastic entity generation scheme. The proposed method is evaluated on real PCB data sets containing 125 images with more than 10.000 splice entities

Dynamic Processor Reconfiguration for Power, Performance and Reliability Management

Technology advancements allowed more transistors to be packed in a smaller area, while the improved performance helped in achieving higher clock frequencies. This, unfortunately led to a power density problem, forcing processor industry to lower the clock frequency and integrate multiple cores on the same die. Depending on core characteristics, the multiple cores in the die could be symmetric or asymmetric. Asymmetric multi-core processors (AMPs) have been proposed as an alternative to symmetric multi-cores to improve power efficiency. AMPs comprise of cores that implement the same ISA, but differ in performance and power characteristics due to varying sizes of micro-architectural resources. As the computational bottleneck of a workload shifts from one resource to another during its course of execution, reassigning it to another core (where it runs more efficiently), can improve the overall power efficiency. Thus achieving high power efficiency in AMPs requires (i) a diverse set of cores that are optimized for various program phases, (ii) runtime analysis to determine the best core to run on, and (iii) low overhead of re-assigning a thread to a different core type. Decisions to swap threads between AMPs are made at coarse grain granularity of millions of instructions, to mitigate the impact of thread migration overhead. But the computational needs of the program rapidly change during the course of its execution. The best core configuration for an application such that, both power consumption and performance are optimized, changes over time rapidly at fine granularity of thousands of instructions. This dissertation explores ways to design core micro-architecture such that high power efficiency could be achieved, if switching overhead could be lowered, enabling fine grain switching. To take advantage of power saving opportunities at fine grain granularity, this thesis explores reconfigurable/morphable architectures where core resources are reconfigured on demand to suit the needs of the executing application. At first, we explore reconfigurable architectures consisting of two kinds of cores: out-of-order (OOO) big cores and in-order (InO) small cores. The big cores provide higher performance while the small cores are more power efficient. In this proposed architecture, OOO core reconfigures into InO core at run time. Our proposed online management scheme decides to switch between these core types such that we obtain significant power benefits without impacting performance. We also observe that, resource requirements of applications can be quite diverse and consequently, resource bottlenecks or excesses can vary considerably. Thus, reconfiguration between just two core modes may not fully exploit power and performance improvement opportunities. We therefore, explore reconfigurable architectures consisting of diverse core types that not limited to big and little cores. A single core can reconfigure into multiple core modes where each mode has unique power and performance characteristics. Workload performance on a particular core mode depends on a large set of processor resources. Some workloads are highly memory intensive, some exhibit large instruction dependency, some experience high rates of branch mis-prediction, while other workloads exhibit large exploitable instruction level parallelism. A diverse set of core modes is needed, that could address shifting resource needs during various program phases of an application. Different trade-offs in power and performance could be achieved by reducing or expanding the size of various resource. Trade-offs for each core mode are also affected by operating voltage and frequency. We therefore, propose joint core resource resizing with dynamic voltage and frequency scaling (DVFS), which is important for applications whose performance is sensitive to changes in frequency. Thus, at fine granularity, the core should adapt to varying instruction window sizes, execution bandwidth and frequency to meet the demands of the workload at run-time to improve power efficiency. Many current processors employ DVFS aggressively to improve power efficiency and maximize performance. This dissertation studies the tradeoff in power efficiency in using fine grain DVFS and reconfigurable architectures mentioned above.We also explore another important problem due to continued scaling of devices which results in higher vulnerability to soft-errors. We consider dynamic core reconfiguration from the perspectives of both power efficiency and vulnerability to soft-errors. An online management scheme is proposed such that core reconfiguration upon a thread switch not only improves power efficiency but also does not increase the vulnerability to soft errors. In summary, we propose in this thesis several solutions for improving power efficiency by integrating heterogeneity within the core. We also address how popular power reduction techniques like DVFS are comparable to our approach. Finally, we address reliability challenges along with improving power efficiency

GoalD: A Goal-Driven Deployment Framework for Dynamic and Heterogeneous Computing Environments

Context: Emerging paradigms like Internet of Things and Smart Cities utilize advanced sensing and communication infrastructures, where heterogeneity is an inherited feature. Applications targeting such environments require adaptability and context-sensitivity to uncertain availability and failures in resources and their ad-hoc networks. Such heterogeneity is often hard to predict, making the deployment process a challenging task. Objective: This paper proposes GoalD as a goal-driven framework to support autonomous deployment of heterogeneous computational resources to fulfill requirements, seen as goals, and their correlated components on one hand, and the variability space of the hosting computing and sensing environment on the other hand. Method: GoalD comprises an offline and an online stage to fulfill autonomous deployment by leveraging the use of goals. Deployment configuration strategies arise from the variability structure of the Contextual Goal Model as an underlying structure to guide autonomous planning by selecting available as well as suitable resources at runtime. Results: We evaluate GoalD on an existing exemplar from the selfadaptive systems community – the Tele Assistance Service provided by Weyns and Calinescu [1]. Furthermore, we evaluate the scalability of GoalD on a repository consisting of 430,500 artifacts. The evaluation results demonstrate the usefulness and scalability of GoalD in planning the deployment of a system with thousands of components in a few milliseconds

A plm implementation for aerospace systems engineering-conceptual rotorcraft design

The thesis will discuss the Systems Engineering phase of an original Conceptual Design Engineering Methodology for Aerospace Engineering-Vehicle Synthesis. This iterative phase is shown to benefit from digitization of Integrated Product&Process Design (IPPD) activities, through the application of Product Lifecycle Management (PLM) technologies. Requirements analysis through the use of Quality Function Deployment (QFD) and 7 MaP tools is explored as an illustration. A "Requirements Data Manager" (RDM) is used to show the ability to reduce the time and cost to design for both new and legacy/derivative designs. Here the COTS tool Teamcenter Systems Engineering (TCSE) is used as the RDM. The utility of the new methodology is explored through consideration of a legacy RFP based vehicle design proposal and associated aerospace engineering. The 2001 American Helicopter Society (AHS) 18th Student Design Competition RFP is considered as a starting point for the Systems Engineering phase. A Conceptual Design Engineering activity was conducted in 2000/2001 by Graduate students (including the author) in Rotorcraft Engineering at the Daniel Guggenheim School of Aerospace Engineering at the Georgia Institute of Technology, Atlanta GA. This resulted in the "Kingfisher" vehicle design, an advanced search and rescue rotorcraft capable of performing the "Perfect Storm" mission, from the movie of the same name. The associated requirements, architectures, and work breakdown structure data sets for the Kingfisher are used to relate the capabilities of the proposed Integrated Digital Environment (IDE). The IDE is discussed as a repository for legacy knowledge capture, management, and design template creation. A primary thesis theme is to promote the automation of the up-front conceptual definition of complex systems, specifically aerospace vehicles, while anticipating downstream preliminary and full spectrum lifecycle design activities. The thesis forms a basis for additional discussions of PLM tool integration across the engineering, manufacturing, MRO and EOL lifecycle phases to support business management processes.M.S.Committee Chair: Schrage, Daniel P.; Committee Member: Costello, Mark; Committee Member: Wilhite, Alan, W

A Dynamic Reconfiguration Framework to Maximize Performance/Power in Asymmetric Multicore Processors

Recent trends in technology scaling have shifted the processing paradigm to multicores. Depending on the characteristics of the cores, the multicores can be either symmetric or asymmetric. Prior research has shown that Asymmetric Multicore Processors (AMPs) outperform their symmetric (SMP) counterparts within a given resource and power budget. But, due to the heterogeneity in core-types and time-varying workload behavior, thread-to-core assignment is always a challenge in AMPs. As the computational requirements vary significantly across different applications and with time, there is a need to dynamically allocate appropriate computational resources on demand to suit the applications’ current needs, in order to maximize the performance and minimize the energy consumption. Performance/power of the applications could be further increased by dynamically adapting the voltage and frequency of the cores to better fit the changing characteristics of the workloads. Not only can a core be forced to a low power mode when its activity level is low, but the power saved by doing so could be opportunistically re-budgeted to the other cores to boost the overall system throughput. To this end, we propose a novel solution that seamlessly combines heterogeneity with a Dynamic Reconfiguration Framework (DRF). The proposed dynamic reconfiguration framework is equipped with Dynamic Resource Allocation (DRA) and Voltage/Frequency Adaptation (DVFA) capabilities to adapt the core resources and operating conditions at runtime to the changing demands of the applications. As a proof of concept, we illustrate our proposed approach using a dual-core AMP and demonstrate significant performance/power benefits over various baselines

Unearthing Strata and Changing Waters: A Landscape for Today

My current practice culminates in generative acts that respond to the objects that I collect from Blacks Run in Harrisonburg, VA. The writing and artworks are extensions of my interest in hybridity and spaces where organic and artificial matter intersect. This thesis provides a conceptual framework for Unearthing Strata and Changing Waters: A Landscape for Today, an MFA body of work by Mallory Burrell

Pattern Process: An Exploration of Non-Architectonic Seams

The re-purposing of a two-hundred year-old river-side factory site involves a complex set of extant, historical, and hypothetical considerations, and requires a system of strategies and tactics beyond the conventional scope of historic preservation or formal architectural analysis. The discovery of cultural patterns, both physical and social, becomes the alibi for an even broader exploration of design methodology. By reviving the etymology of "pattern" as the co-joining of autonomous pieces to create form and volume, a conceptual study of pattern and seams seeks to develop an implicit methodology that first reveals non-architectonic structural relationships, then engages these structures as determinants in the re-design of the existing built environment. The proposed framework is tested against an architectural agenda that seams historic patterns of human activity and site conditions with speculative patterns of event, process, and technology for the creation of a place expressing contemporary ideology among the continuity of living history

A Worldwide State-of-the-Art Analysis for Bus Rapid Transit: Looking for the Success Formula

This paper’s intended contribution, in terms of providing an additional angle in the existing Bus Rapid Transit (BRT) state-of-the-art knowledge spectrum, is a dual one. On the one hand, it provides a detailed description of the mode, re-defining BRT as an overall concept by identifying, discussing, and categorizing in a systematic way its strengths and its weaknesses in comparison with rail-based solutions and conventional bus services. On the other hand, it presents in detail a number of selected scheme-oriented applications from around the world, looking into some of the basic ingredients behind BRT’s success (or failure) stories. This is a scientific effort that could inform the reader about the current status of BRT internationally and about the challenges and opportunities that exist when trying to materialize BRT’s potential as an effective urban passenger solution that could challenge the merits of more conventional mass-transit options

Rescuing urban regeneration from urban patronage: towards inclusive development in the Voortrekker Road Corridor

The Voortrekker Road Corridor in Cape Town was recently identified as an Integration Zone according to National Treasury's Integrated City Development Grant (ICDG). Prior to this a number of private and public stakeholders founded the Greater Tygerberg Partnership, in response to the need for a coordinating body to champion inclusive regeneration and local economic development in the corridor and neighbouring northern suburbs. Funded wholly by the City of Cape Town for its first three years of operation, the Partnership had after two years in operation appeared to have made little progress in catalysing interest and tangible investment in the area, even on a micro level. This dissertation utilises the qualitative analysis method of process tracing for the period of 2012-2015 to explore themes of urban governance and conversely urban patronage. It firstly considers whether the apparent stasis is due to the Partnership being subjected to capture by strong private and political elites. Subsequently it examines whether incremental, micro-level governance initiatives and acts of public entrepreneurship, though seemingly small, have the potential to build momentum capable of overcoming such threatening predatory networks, and in so doing redirect the organisation towards achieving substantive inclusive and equitable regeneration