Arithmetic with the Two-Dimensional Logarithmic Number System (2DLNS)

The ever increasing demand for low power DSP applications has directed researchers to contemplate a variety of potential approaches in different contexts. Since DSP algorithms heavily rely on multiplication, there are growing demands for more efficient multiplication structures. In this regard, using some alternative number systems, which inherently are capable of reducing the hardware complexity, have been studied. The Multi-Dimensional Logarithmic Number System (MDLNS), a multi-digit and multi-base extension to the Logarithmic Number System (LNS), is considered as an alternative to the traditional binary representation for selected applications. The MDLNS provides a reduction in the size of the number representation with a non-linear mapping and promises a lower cost realization of arithmetic operations with a reduced hardware complexity. In addition, using the recursive multiplication technique, which refers to the published multiplication algorithm that uses smaller multipliers to implement a larger operation, reduces the size of operands and corresponding partial additions. As part of this research, 2DLNS-based multiplication architectures with two different levels of recursion are presented. These architectures combine some of the exibility of software with the high performance of hardware by implementing the recursive multiplication schemes on a 2DLNS processing structure. These implementations demonstrate the efciency of 2DLNS in DSP applications and show outvistanding results in terms of operation delay and dynamic power consumption. We also demonstrate the application of recursive 2DLNS multipliers to reconfigurable multiplication architectures. These architectures are able to perform single and double precision multiplication, as well as fault tolerant and dual throughput single precision operations. Modern DSP processors, such as those used in hand-held devices, may find considerable benefit from these high-performance, low-power, and high-speed recongurable architectures. In the final part of this research work, recursive 2DLNS multiplication architectures have been applied to a FIR lter structure. These implementations show considerable improvement to their binary counterparts in terms of VLSI area and power consumption

Difficult operations in the multi-dimensional logarithmic number system.

The Multi-Dimensional Logarithmic Number System (MDLNS), with similar properties to the Logarithmic Number System (LNS), provides more degrees of freedom than the LNS by virtue of having two or more orthogonal bases and the ability to use multiple digits. Unlike the LNS there is no direct functional relationship between binary/floating point representation and the MDLNS representation. Traditionally look-up tables (LUTs) were used to move from the binary domain to the MDLNS domain. This method could be unrealistic for hardware implementation when large binary ranges or multiple digits were used. The lack of this direct relationship also complicated the addition and subtraction operations in MDLNS. Again LUTs were used to perform these operations but they could become unrealistically large when multiple digits or large index ranges were used. The work presented in this thesis describes efficient techniques for implementing difficult MDLNS operations such as binary to MDLNS conversion as well as addition and subtraction. These techniques require the use of a new memory device with range addressing capabilities, a RALUT (range addressable look-up table). The RALUT reduces the exponential complexity associated with the traditional use of potentially large LUTs by physically removing redundant hardware used to store the MDLNS conversion, addition, and subtraction information. Other significant MDLNS improvements such as choosing efficient and optimal bases, the one-bit sign architecture, and single-digit MDLNS RALUT reduction are also discussed. These improvements are shown to reduce the hardware implementation and improve performance without sacrificing any of the MDLNS accuracy.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2003 .M87. Source: Dissertation Abstracts International, Volume: 65-01, Section: B, page: 0365. Adviser: Graham Arnold Jullien. Thesis (Ph.D.)--University of Windsor (Canada), 2003

Novel arithmetic implementations using cellular neural network arrays.

The primary goal of this research is to explore the use of arrays of analog self-synchronized cells---the cellular neural network (CNN) paradigm---in the implementation of novel digital arithmetic architectures. In exploring this paradigm we also discover that the implementation of these CNN arrays produces very low system noise; that is, noise generated by the rapid switching of current through power supply die connections---so called di/dt noise. With the migration to sub 100 nanometer process technology, signal integrity is becoming a critical issue when integrating analog and digital components onto the same chip, and so the CNN architectural paradigm offers a potential solution to this problem. A typical example is the replacement of conventional digital circuitry adjacent to sensitive bio-sensors in a SoC Bio-Platform. The focus of this research is therefore to discover novel approaches to building low-noise digital arithmetic circuits using analog cellular neural networks, essentially implementing asynchronous digital logic but with the same circuit components as used in analog circuit design. We address our exploration by first improving upon previous research into CNN binary arithmetic arrays. The second phase of our research introduces a logical extension of the binary arithmetic method to implement binary signed-digit (BSD) arithmetic. To this end, a new class of CNNs that has three stable states is introduced, and is used to implement arithmetic circuits that use binary inputs and outputs but internally uses the BSD number representation. Finally, we develop CNN arrays for a 2-dimensional number representation (the Double-base Number System - DBNS). A novel adder architecture is described in detail, that performs the addition as well as reducing the representation for further processing; the design incorporates an innovative self-programmable array. Extensive simulations have shown that our new architectures can reduce system noise by almost 70dB and crosstalk by more than 23dB over standard digital implementations.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2005 .I27. Source: Dissertation Abstracts International, Volume: 66-11, Section: B, page: 6159. Thesis (Ph.D.)--University of Windsor (Canada), 2005