An Architecture for On board Frequency Domain Analysis of Launch Vehicle Vibration Signals

The dynamic properties of the airborne structures plays a crucial role in the stability of the vehicle during flight. Modal and spectral behaviour of the structures are simulated and analysed. Ground tests are carried out with environmental conditions close to the flight conditions, with some assumptions. Subsequently, based on the flight telemetered data, the on-board mission algorithm and the auto-pilot filter coefficients are fine tuned. An attempt is made in this paper to design a novel architecture for analysing the modal and spectral random vibration signals on-board the flight vehicle and to identify the dominant frequencies. Based on the analysed results, the mission mode algorithm and the filter coefficients can be fine tuned on-board for better effectiveness in control and providing more stability. Three types of windows viz. Hann, Hamming and Blackman-Harris are configured with a generalised equation using FIR filter structure. The overlapping of the input signal data for better inclusiveness of the real-time data is implemented with BRAM. The domain conversion of the data from time domain to frequency domain is carried out with FFT using Radix-2 BF architecture. The FFT output data are processed for calculating the power spectral density. The dominant frequency is identified using the array search method and Goldschmidt algorithm is utilised for the averaging of the PSDs for better precision. The proposed architecture is synthesised, implemented and tested with both Synthetic and doppler signal of 300 Hz spot frequency padded with Gaussian white noise. The results are highly satisfactory in identifying the spot frequency and generating the PSD array

Simulation of Parallel Pipeline Radix 2^2 Architecture

In popular orthogonal frequency division multiplexing (OFDM) communication system processing is one of the key procedures Fast Fourier transform (FFT) and inversely for that Fast Fourier Transform (IFFT) is one of them. In this VLSI implementation Structured pipeline architectures, low power consumption, high speed and reduced chip area are the important concerns. In this paper, presentation of the worthy implementation of FFT/IFFT processor for OFDM applications is described. We obtain the single-path delay feedback architecture, to get a ROM of smaller size and this proposed architecture applies a reconfigurable complex multiplier. To minimize the error of truncation we apply a fixed width modified booth multiplier. As a result, the proposed radix-2k feed forward architectures even offer an attractive solution for current applications, and also open up a new research line on feed forward structures

A Low-Latency FFT-IFFT Cascade Architecture

This paper addresses the design of a partly-parallel cascaded FFT-IFFT architecture that does not require any intermediate buffer. Folding can be used to design partly-parallel architectures for FFT and IFFT. While many cascaded FFT-IFFT architectures can be designed using various folding sets for the FFT and the IFFT, for a specified folded FFT architecture, there exists a unique folding set to design the IFFT architecture that does not require an intermediate buffer. Such a folding set is designed by processing the output of the FFT as soon as possible (ASAP) in the folded IFFT. Elimination of the intermediate buffer reduces latency and saves area. The proposed approach is also extended to interleaved processing of multi-channel time-series. The proposed FFT-IFFT cascade architecture saves about N/2 memory elements and N/4 clock cycles of latency compared to a design with identical folding sets. For the 2-interleaved FFT-IFFT cascade, the memory and latency savings are, respectively, N/2 units and N/2 clock cycles, compared to a design with identical folding sets