High efficiency power amplifiers for modern mobile communications: The load-modulation approach

Modern mobile communication signals require power amplifiers able to maintain very high efficiency in a wide range of output power levels, which is a major issue for classical power amplifier architectures. Following the load-modulation approach, efficiency enhancement is achieved by dynamically changing the amplifier load impedance as a function of the input power. In this paper, a review of the widely-adopted Doherty power amplifier and of the other load-modulation efficiency enhancement techniques is presented. The main theoretical aspects behind each method are introduced, and the most relevant practical implementations available in recent literature are reported and discussed

Advanced High Efficiency Architectures for Next Generation Wireless Communications

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Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

Power Amplifiers for Next Generation Wireless Platforms

Class-E amplifier has the potential to deliver high efficiency required for the next generation wireless systems. In this journal, we discuss a novel load pull analysis technique to characterize the efficiency performance of Class-E amplifier in an outphasing power combining scheme. Class-E amplifier is not an ideal current or voltage source as is required for the traditional analysis of outphasing structures. It requires a phase modulated input signal and has a non-linear transfer characteristic which is a function of load impedance. Here we define an operating load locus based on the load pull analysis which can be used to predict the non-linear transfer function, efficiency, output power, input drive phase and many other factors associated with the outphasing class-E amplifier. This scheme could also be used to characterize any amplifier class in an outphasing structure. Finally modulation performance of Class-E amplifier using PWM technique is also presented

RF and Millimeter-wave Techniques to Improve Scalability and Efficiency of Digital Beamforming Arrays

Spectrum overcrowding, ever increasing demand for high data rate and increased mobility requirements are three major challenges 5G-technology is trying to address. In this thesis I start with a RF front-end technique that deals with blocker interference arising from spectrum overcrowding both across frequency bands and within the same frequency bands. Chapter 3 presents a single wire IF interface design for phased array receivers which enables simple IF backhaul for high data volume MIMO systems. Finally a outphasing power amplifier(PA) design is presented in chapter 4 along with a driver amplifier with digital amplitude modulation to achieve state of the art power back off efficiency, which reduces battery usage and thus increases mobility. The first part of this thesis demonstrates the use of orthogonal sequences along to N-path filters to achieve reconfigurable select/reject filtering of signals based on their spatial, spectral and code-domain properties. A frequency/code-domain reject and select filtering is proposed and implemented using N-path switching with passive inductors as correlators. Using inductors instead of capacitors in N-path filters is challenging because of large inductance value required for our application demands use of off-chip inductors, which comes with associated parasitics and lower self-resonance frequency. In this design a cascaded inductor approach and differential N-path filtering is used to overcome inductor parasitics and enable operation at 1 GHz. A code-domain notch filter followed by a code-domain select receiver is designed and implemented in 65-nm CMOS technology. Measurements demonstrate 0.5 GHz to 1.0 GHz filter tuning range, with a maximum 26dB rejection for a blocker signal with 8dBm power, while consuming 60mW (at 1GHz operation frequency) and occupying 1.2mm2 of die area. Second part of this thesis demonstrates a single wire IF interface to simplify scaling of millimeter-wave(mm-Wave) phased array systems while preserving the data from each element, this enables spatial multiplexing, virtual arrays for radar, digital beamforming(DBF), etc. However, per-element digitization results in a formidable I/O challenge in large-scale tiled MIMO mm-Wave arrays. This dissertation demonstrates a 28 GHz 4-element MIMO RX with a single-wire interface that multiplexes the baseband signals of all elements and the LO reference through code-domain multiplexing. System considerations are presented and the approach is validated through DBF after de-multiplexing of the baseband signals from the single wire. Each element in the array achieves 16 dB conversion gain and ∼ 7 dB noise figure(NF) while consuming 60 mA from 1.2 V. The IC occupies 5.75 mm² in 65-nm CMOS. Final part of this thesis describes the design and implementation of a digital outphasing PA at 28 GHz to achieve state of the art back of efficiency. Outphasing PA require branch PA units to act as voltage sources(very low output impedance), which is challenging at mm-Wave frequencies. In this PA design an approximate class-F operation is achieved by tuning PA load network for up to 3rd harmonic. A stacked PA architecture is used for individual PA units to achieve high maximum power output. Output-power further improved by utilizing a novel diode connected stack bias circuit to improve out-put swing. PA delivers a maximum output-power of 20 dBm with a peak power added efficiency(PAE) of 27% (PA along with driver stages) and 6 dB back-off PAE of 16.5%

Analytical Approaches to Load Modulation Power Amplifier Design

In future mobile communication networks, there will be a shift toward higher carrier frequencies and highly integrated multiple antenna systems. The system performance will largely depend on the available radio frequency (RF) hardware. As such, RF power amplifiers (PAs) with improved performance, e.g. energy efficiency, are needed. Active load modulation (ALM) is one of the most common PA efficiency enhancement techniques. Unfortunately, different ALM techniques come at the cost of degrading other PA attributes. Through investigation of new ALM design techniques, the overall objective of this thesis is to improve upon different attributes and performance trade-offs in ALM PAs for future wireless systems.\ua0The working principle of ALM PAs is determined by both how the individual transistors are operated and how their outputs are combined. In the first part of the thesis, an analytical approach, where the output combiner is assumed to be an arbitrary black-box, is applied to the Doherty PA. The fundamental interaction between the main and auxiliary transistors is analyzed and generalized. New solutions with improved performance are identified, such as higher gain and an improved efficiency-linearity trade-off. This approach also introduces improved integration possibilities, which are demonstrated by a transmitter where the antenna acts as both the radiator and the Doherty combiner. Additionally, the analytical approach is applied to an isolated two-way power divider. This unlocks many new possibilities, such as improved integration and layout flexibility. \ua0In the second part, one embodiment of the emerging ALM architecture, the load modulated balanced amplifier (LMBA), is proposed: the RF-input Doherty-like LMBA. Design equations are derived and the fundamental operation is studied. This variant presents several advantages over other known architectures, such as higher gain and device periphery scaling of the different transistors.\ua0The third part proposes a new measurement-based ALM PA design procedure, which emulates the full behavior of the transistors in any ALM architecture using active load-pull measurements. This method can predict the intricate behavior in ALM PAs and it gives measurement-based insights into the internal operation of the circuit already at the design stage. This facilitates the design for optimal ALM PA performance. \ua0The thesis contributes with several promising techniques for reducing performance trade-offs and improving the overall performance of ALM PAs. Therefore, the results will contribute to the development of more energy efficient and high capacity wireless services in the future

Contribution to dimensionality reduction of digital predistorter behavioral models for RF power amplifier linearization

The power efficiency and linearity of radio frequency (RF) power amplifiers (PAs) are critical in wireless communication systems. The main scope of PA designers is to build the RF PAs capable to maintain high efficiency and linearity figures simultaneously. However, these figures are inherently conflicted to each other and system-level solutions based on linearization techniques are required. Digital predistortion (DPD) linearization has become the most widely used solution to mitigate the efficiency versus linearity trade-off. The dimensionality of the DPD model depends on the complexity of the system. It increases significantly in high efficient amplification architectures when considering current wideband and spectrally efficient technologies. Overparametrization may lead to an ill-conditioned least squares (LS) estimation of the DPD coefficients, which is usually solved by employing regularization techniques. However, in order to both reduce the computational complexity and avoid ill-conditioning problems derived from overparametrization, several efforts have been dedicated to investigate dimensionality reduction techniques to reduce the order of the DPD model. This dissertation contributes to the dimensionality reduction of DPD linearizers for RF PAs with emphasis on the identification and adaptation subsystem. In particular, several dynamic model order reduction approaches based on feature extraction techniques are proposed. Thus, the minimum number of relevant DPD coefficients are dynamically selected and estimated in the DPD adaptation subsystem. The number of DPD coefficients is reduced, ensuring a well-conditioned LS estimation while demanding minimum hardware resources. The presented dynamic linearization approaches are evaluated and compared through experimental validation with an envelope tracking PA and a class-J PA The experimental results show similar linearization performance than the conventional LS solution but at lower computational cost.La eficiencia energetica y la linealidad de los amplificadores de potencia (PA) de radiofrecuencia (RF) son fundamentales en los sistemas de comunicacion inalambrica. El principal objetivo a alcanzar en el diserio de amplificadores de radiofrecuencia es lograr simultaneamente elevadas cifras de eficiencia y de linealidad. Sin embargo, estas cifras estan inherentemente en conflicto entre si, y se requieren soluciones a nivel de sistema basadas en tecnicas de linealizacion. La linealizacion mediante predistorsion digital (DPD) se ha convertido en la solucion mas utilizada para mitigar el compromise entre eficiencia y linealidad. La dimension del modelo del predistorsionador DPD depende de la complejidad del sistema, y aumenta significativamente en las arquitecturas de amplificacion de alta eficiencia cuando se consideran los actuales anchos de banda y las tecnologfas espectralmente eficientes. El exceso de parametrizacion puede conducir a una estimacion de los coeficientes DPD, mediante minimos cuadrados (LS), mal condicionada, lo cual generalmente se resuelve empleando tecnicas de regularizacion. Sin embargo, con el fin de reducir la complejidad computacional y evitar dichos problemas de mal acondicionamiento derivados de la sobreparametrizacion, se han dedicado varies esfuerzos para investigar tecnicas de reduccion de dimensionalidad que permitan reducir el orden del modelo del DPD. Esta tesis doctoral contribuye a aportar soluciones para la reduccion de la dimension de los linealizadores DPD para RF PA, centrandose en el subsistema de identificacion y adaptacion. En concrete, se proponen varies enfoques de reduccion de orden del modelo dinamico, basados en tecnicas de extraccion de caracteristicas. El numero minimo de coeficientes DPD relevantes se seleccionan y estiman dinamicamente en el subsistema de adaptacion del DPD, y de este modo la cantidad de coeficientes DPD se reduce, lo cual ademas garantiza una estimacion de LS bien condicionada al tiempo que exige menos recursos de hardware. Las propuestas de linealizacion dinamica presentados en esta tesis se evaluan y comparan mediante validacion experimental con un PA de seguimiento de envolvente y un PA tipo clase J. Los resultados experimentales muestran unos resultados de linealizacion de los PA similares a los obtenidos cuando se em plea la solucion LS convencional, pero con un coste computacional mas reducido.Postprint (published version

Novel Predistortion System for 4G/5G Small-Cell and Wideband Transmitters

To meet the growing demand for mobile data, various technologies are being introduced to wireless networks to increase system capacity. On one hand, large number of small-cell base stations are adopted to serve the reduced cell size; on the other hand, millimeter wave (mm-wave) systems with large antenna arrays that transmit ultra-wideband signals are expected in fifth generation (5G) networks. Power amplifiers (PAs), responsible for boosting the radio frequency (RF) signal power, are the most critical components in base station transmitters, and dominate the overall efficiency and linearity of the system. The design challenges to balance the contradictory requirements of efficiency and linearity of the PAs are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solutions face increasing difficulties keeping up with new developments in base station technologies. When considering sub-6 GHz small-cell base station transmitters, analog and RF predistortion techniques have recently received renewed attention due to their inherent low power nature. Their achievable linearization capacity is significantly limited, however, largely by their implementation complexity in realizing the needed predistortion models in analog circuitry. On the other hand, despite significant developments in DPD models for wideband signals, the implementations of such DPD models in practical hardware have received relatively little attention. Yet the conventional implementation of a DPD engine is limited by the maximum clock frequency of the digital circuitry employed and cannot be scaled to satisfy the growing bandwidth of transmitted signals for 5G networks. Furthermore, both analog and digital solutions require a transmitter-observation-receiver (TOR) to capture the PA outputs, necessitates the use of analog-to-digital converters (ADCs) whose complexity and power consumption increase with signal bandwidth. Such trend is not scalable for future base stations, and new innovations in feedback and training methods are required. This thesis presents a number of contributions to address the above identified challenges. To reduce the power overhead of the linearization system, a digitally-assisted analog-RF predistortion (DA-ARFPD) system that uses a novel predistortion model is introduced. The proposed finite-impulse-response assisted envelope memory polynomial (FIR-EMP) model allows for a reduction of hardware implementation complexity while maintaining good linearization capacity and low power overhead. A two-step small-signal-assisted parameter identification (SSAPI) algorithm is devised to estimate the parameters of the two main blocks of the FIR-EMP model, such that the training can be completed efficiently. A DA-ARFPD test bench has been built, which incorporates major RF components, to assess the validity of the proposed FIR-EMP scheme and the SSAPI algorithm. Measurement results show that the proposed FIR-EMP model with SSAPI algorithm can successfully linearize multiple PAs driven with various wideband and carrier-aggregated signals of up to 80~MHz modulation bandwidths for sub-6 GHz systems. Next, a hardware-efficient real-time DPD system with scalable linearization bandwidth for ultra-wideband 5G mm-wave transmitters is proposed. It uses a novel parallel-processing DPD engine architecture to process multiple samples per clock cycle, overcomes the linearization bandwidth limit imposed by the maximum clock rate of digital circuits used in conventional DPD implementation. Potentially unlimited linearization bandwidth could be achieved by using the proposed system with current digital circuit technologies. The linearization performance and bandwidth scalability of the proposed system is demonstrated experimentally using a silicon-based Doherty (DPA) with 400 MHz wideband signal operating at 28 GHz, and over-the-air measurements using a 64-element beamforming array with 800 MHz wideband signal, also at 28 GHz. The proposed DPD system achieves over 2.4 GHz linearization bandwidth using only a 300 MHz core clock for the digital circuits. Finally, to reduce the power consumption and cost of the TOR, a new approach to train the predistorter using under-sampled feedback signal is presented. Using aliased samples of the PA's output captured at either baseband or intermedia frequency (IF), the proposed algorithm is able to compute the coefficients of the predistortion engine to linearize the PA using a direct learning architecture. Experimentally, both the baseband and IF schemes achieve linearization performance comparable to a full-rate system. Implemented together with a parallel-processing based DPD engine on a field-programmable gate array (FPGA) based system-on-chip (SOC), the proposed feedback and training solution achieves over 2.4~GHz linearization bandwidth using an ADC operating at a clock rate of 200 MHz. Its performance is demonstrated experimentally by linearizing a silicon DPA with 200 MHz and 400 MHz signals in conductive measurements, and a 64-element beamforming array with 400 MHz and 800 MHz signals in over-the-air testing