Jefferson Digital Commons quarterly report: April-June 2019

This quarterly report includes: Articles CREATE Day Presentations Dissertations From the Archives Grand Rounds and Lectures House Staff Quality Improvement and Patient Safety Posters JCIPE Student Hotspotting Posters Journals and Newsletters MPH Capstone Presentations Posters Sigma Xi Research Day What People are Saying About the Jefferson Digital Common

Supporting community engagement through teaching, student projects and research

The Education Acts statutory obligations for ITPs are not supported by the Crown funding model. Part of the statutory role of an ITP is “... promotes community learning and by research, particularly applied and technological research ...” [The education act 1989]. In relation to this a 2017 TEC report highlighted impaired business models and an excessive administrative burden as restrictive and impeding success. Further restrictions are seen when considering ITPs attract < 3 % of the available TEC funding for research, and ~ 20 % available TEC funding for teaching, despite having overall student efts of ~ 26 % nationally. An attempt to improve performance and engage through collaboration (community, industry, tertiary) at our institution is proving successful. The cross-disciplinary approach provides students high level experience and the technical stretch needed to be successful engineers, technologists and technicians. This study presents one of the methods we use to collaborate externally through teaching, student projects and research

Estimates of persistent inward current in human motor neurons during postural sway

Persistent inward current (PIC) is a membrane property critical for increasing gain of motor neuron output. In humans, most estimates of PIC are made from plantarflexor or dorsiflexor motor units with the participant in a seated position with the knee flexed. This seated and static posture neglects the task-dependent nature of the monoaminergic drive that modulates PIC activation. Seated estimates may drastically underestimate the amount of PIC that occurs in human motor neurons during functional movement. The current study estimated PIC using the conventional paired motor unit technique which uses the difference between reference unit firing frequency at test unit recruitment and reference unit firing frequency at test unit de-recruitment (∆F) during triangular-shaped, isometric ramps in plantarflexion force as an estimate of PIC. Estimates of PIC were also made during standing anterior postural sway, a postural task that elicits a ramped increase and decrease in soleus motor unit activation similar to the conventional seated ramp contractions. For each motor unit pair, ∆F estimates of PIC made during conventional isometric ramps in the seated posture were compared to those made during standing postural sway. Baseline reciprocal inhibition (RI) was also measured in each posture using the post-stimulus time histogram (PSTH) technique. Hyperpolarizing input has been shown to have a reciprocal relationship with PIC in seated posture and RI was measured to examine if the same reciprocal relationship holds true during functional PIC estimation. It was hypothesized that an increase in ∆F would be seen during standing compared to sitting due to greater neuromodulatory input. We found that ∆F estimates during standing postural sway were equal (2.44 ± 1.17, p=0.44) to those in seated PIC estimates (2.73± 1.20) using the same motor unit pair. Reciprocal inhibition was significantly lower when measured in a standing posture (0.0031 ± 0.0251,

Asynchronous techniques for system-on-chip design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed