Architectures and Integrated Circuits for Efficient, High-power "Digital'' Transmitters for Millimeter-wave Applications

This thesis presents architectures and integrated circuits for the implementation of energy-efficient, high-power "digital'' transmitters to realize high-speed long-haul links at millimeter-wave frequencies in nano-scale silicon-based processes

Doctor of Philosophy

dissertationHigh speed wireless communication systems (e.g., long-term evolution (LTE), Wi-Fi) operate with high bandwidth and large peak-to-average power ratios (PAPRs). This is largely due to the use of orthogonal frequency division multiplexing (OFDM) modulation that is prevalent to maximize the spectral efficiency of the communication system. The power amplifier (PA) in the transmitter is the dominant energy consumer in the radio, largely because of the PAPR of the input signal. To reduce the energy consumption of the PA an amplifier that simultaneously achieves high efficiency and high linearity. Furthermore, to lower the cost for high volume production, it is desirable to achieve a complete System-on-Chip (SoC) integration. Linear amplifiers (e.g., Class-A, -B, -AB) are inefficient when amplifying signals with large PAPR that is associated by high peak-to-average modulation techniques such as LTE. OFDM. Switching amplifiers (e.g., Class-D, -E, -F) are very promising due to their high efficiency when compared to their linear amplifier counterparts. Linearization techniques for switching amplifiers have been intensively investigated due to their limited sensitivity to the input amplitude of the signal. Deep-submicron CMOS technology is mostly utilized for logic circuitry, and the Moore's law scaling of CMOS optimizes transistors to operate as high-speed and low-loss switches rather than high gain transistors. Hence, it is advantageous to use transistors in switching mode as switching amplifies and use high-speed digital logic circuitry to implement linearization systems and circuitry. In this work, several linearization architectures are investigated and demonstrated. An envelope elimination and restoration (EER) transmitter that comprises a class-E power amplifier and a 10-bit digital-to-analog converter (DAC) controlled current modulator is investigated. A pipelined switched-capacitor DAC is designed to control an open-loop transconductor that operates as a current modulator, modulating the amplitude of the current supplied to a class-E PA. Such a topology allows for increased filtering of the quantization noise that is problematic in most digital PAs (DPA). The proposed quadrature and multiphase architecture can avoid the bandwidth expansion and delay mismatch associated with polar PAs. The multiphase switched capacitor power amplifier (SCPA) was proposed after the quadrature SCPA and it significantly improves the power efficiency

Digital Radio Encoding and Power Amplifier Design for Multimode and Multiband Wireless Communications

The evolution of wireless technology has necessitated the support of multiple communication standards by mobile devices. At present, multiple chipsets/radios operating at predefined sets of modulation schemes, frequency bands, bandwidths and output power levels are used to achieve this objective. This leads to higher component counts, increased cost and limits the capacity to cope with future communication standards. In order to tackle different wireless standards using a single chipset, digital circuits have been increasingly deployed in radios and demonstrated re-configurability in different modulation schemes (multimode) and frequency bands (multiband). Despite efforts and progress made in digitizing the entire radio, the power amplifier (PA) is still designed using an conventional approach and has become the bottleneck in digital transmitters, in terms of low average power efficiency, poor compatibility with modern CMOS technology and limited re-configurability. This research addresses these issues from two aspects. The first half of the thesis investigates signal encoding issues between the modulator and PA. We propose, analyze and evaluate a new hybrid amplitude/time signal encoding scheme that significantly improves the coding efficiency and dynamic range of a digitally modulated power amplifier (DMPA) without significantly increasing design complexity. The proposed hybrid amplitude/time encoding scheme combines both the amplitude domain and the time domain to optimally encode information. Experimental results show that hybrid amplitude/time encoding results in a 35% increase in the average coding efficiency with respect to conventional time encoding, and is only 6.7% lower than peak efficiency when applied to a Wireless Local Area Network (WLAN) signal with a peak to average power ratio equal to 9.9 dB. A new DMPA architecture, based on the proposed hybrid encoding, is also proposed. The second half of this thesis presents the design, analysis and implementation of a CMOS PA that is amenable to the proposed hybrid encoding scheme. A multi-way current mode class-D PA architecture has been proposed and realized in 130 nm CMOS technology. The designed PA has satisfied the objectives of wide bandwidth (1.5 GHz - 2.7 GHz at 1 dB output power), and high efficiency (PAE 63%) in addition to demonstrating linear responses using the proposed digital encoding. A complete digital transmitter combining the encoder and the multi-way PA was also investigated. The overall efficiency is 27% modulating 7.3 dB peak to average power ratio QAM signals

A Survey of Positioning Systems Using Visible LED Lights

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.As Global Positioning System (GPS) cannot provide satisfying performance in indoor environments, indoor positioning technology, which utilizes indoor wireless signals instead of GPS signals, has grown rapidly in recent years. Meanwhile, visible light communication (VLC) using light devices such as light emitting diodes (LEDs) has been deemed to be a promising candidate in the heterogeneous wireless networks that may collaborate with radio frequencies (RF) wireless networks. In particular, light-fidelity has a great potential for deployment in future indoor environments because of its high throughput and security advantages. This paper provides a comprehensive study of a novel positioning technology based on visible white LED lights, which has attracted much attention from both academia and industry. The essential characteristics and principles of this system are deeply discussed, and relevant positioning algorithms and designs are classified and elaborated. This paper undertakes a thorough investigation into current LED-based indoor positioning systems and compares their performance through many aspects, such as test environment, accuracy, and cost. It presents indoor hybrid positioning systems among VLC and other systems (e.g., inertial sensors and RF systems). We also review and classify outdoor VLC positioning applications for the first time. Finally, this paper surveys major advances as well as open issues, challenges, and future research directions in VLC positioning systems.Peer reviewe

High Capacity Fiber-Connected Wireless MIMO Communication

There will be more and more users while beyond-5G (B5G) and 6G bring more wireless applications. Current cellular communication networks assign specific serving boundaries for each radio, which becomes a limitation when too many users work with one radio simultaneously. By physically distributing radios. user’s service can be more uniform. Radio-over-fiber is a promising enabling technology for distributed antenna systems.To have several tens of Gbit/s data rate, we need to apply millimeter-wave (mm-wave) frequency band in radio-over-fiber (RoF). However, mm-wave signals have weak penetration and high propagation loss. Hence, beamforming and/or multiple-input-multiple-output (MIMO) technology become necessary for mm-wave RoF to overcome those drawbacks.This thesis introduces an automatic distributed MIMO (D-MIMO) testbed with a statistical MIMO capacity analysis for an indoor use case. Raytracing-based simulations also predicts the indoor case to make a comparison. The statistical MIMO capacity analysis shows that D-MIMO has a higher and more uniform capacity than co-located MIMO (C-MIMO) in measurements and simulations.Next, a mm-wave sigma-delta-over-fiber (SDoF) link architecture is proposed for MIMO applications. In the implementation of this link, a QSFP28 fiber link connects a central unit with a remote radio unit with four bandpass sigma-delta-modulation (BPSDM) bitstreams. The remote radio unit generates four mm-wave signals from four BPSDM signals and feeds a linear array antenna. The measurement characterizes the remote radio head at each stage and concludes that this proposed link can reach 800 Msym/s data rate with -0.5 dBm output bandpower.Furthermore, the proposed link is demonstrated with digital beamforming and multi-user MIMO (MU-MIMO) functionalities. The digital beamforming function reaches 700 Msym/s with -25 dB error vector magnitude (EVM) results by improving the received bandpower in comparison to (single-input-single-output) SISO results. The MU-MIMO function serves two independent users at 500 Msym/s symbol rate and satisfies 3GPP requirements at 1 m over-the-air distance.In conclusion, this thesis proves that D-MIMO has a higher and more uniform capacity than C-MIMO by statistical analysis from measurements and simulations. The proposed novel mm-wave SDoF link can pave the way for future D-MIMO applications

Near-Field Communications: A Comprehensive Survey

Multiple-antenna technologies are evolving towards large-scale aperture sizes, extremely high frequencies, and innovative antenna types. This evolution is giving rise to the emergence of near-field communications (NFC) in future wireless systems. Considerable attention has been directed towards this cutting-edge technology due to its potential to enhance the capacity of wireless networks by introducing increased spatial degrees of freedom (DoFs) in the range domain. Within this context, a comprehensive review of the state of the art on NFC is presented, with a specific focus on its 1) fundamental operating principles, 2) channel modeling, 3) performance analysis, 4) signal processing, and 5) integration with other emerging technologies. Specifically, 1) the basic principles of NFC are characterized from both physics and communications perspectives, unveiling its unique properties in contrast to far-field communications. 2) Based on these principles, deterministic and stochastic near-field channel models are investigated for spatially-discrete (SPD) and continuous-aperture (CAP) antenna arrays. 3) Rooted in these models, existing contributions on near-field performance analysis are reviewed in terms of DoFs/effective DoFs (EDoFs), power scaling law, and transmission rate. 4) Existing signal processing techniques for NFC are systematically surveyed, encompassing channel estimation, beamforming design, and low-complexity beam training. 5) Major issues and research opportunities associated with the integration of NFC and other emerging technologies are identified to facilitate NFC applications in next-generation networks. Promising directions are highlighted throughout the paper to inspire future research endeavors in the realm of NFC.Comment: 56 pages, 23figures; submit for possible journa

Analysis and Design of a Transmitter for Wireless Communications in CMOS Technology

The number of wireless devices has grown tremendously over the last decade. Great technology improvements and novel transceiver architectures and circuits have enabled an astonishingly expanding set of radio-frequency applications. CMOS technology played a key role in enabling a large-scale diffusion of wireless devices due to its unique advantages in cost and integration. Novel digital-intensive transceivers have taken full advantage of CMOS technology scaling predicted by Moore's law. Die-shrinking has enabled ubiquitous diffusion of low-cost, small form factor and low power wireless devices. However, Radio Frequency (RF) Power Amplifiers (PA) transceiver functionality is historically implemented in a module which is separated from the CMOS core of the transceiver. The PA is traditionally dictating power and battery life of the transceiver, thus justifying its implementation in a tailored technology. By contrast, a fully integrated CMOS transceiver with no external PA would hugely benefit in terms of reduced area and system complexity. In this work, a fully integrated prototype of a Switched-Capacitor Power Amplifier (SCPA) has been implemented in a 28nm CMOS technology. The SCPA provides the functionalities of a PA and of a Radio-Frequency Digital-to-Analog Converter (RF-DAC) in a monolithic CMOS device. The switching output stage of the SCPA enables this circuital topology to reach high efficiencies and offers excellent power handling capabilities. In this work, the properties of the SCPA are analyzed in an extensive and detailed dissertation. Nowadays Wireless Communications operate in a very crowded spectrum, with strict coexistence requirements, thus demanding a strong linearity to the RF-DAC section of the SCPA. A great part of the work of designing a good SCPA is in fact designing a good RF-DAC. To enhance RF-DAC linearity, a precision of the timing of the elements up to the ps range is required. The use of a single core-supply voltage in the whole circuit including the CMOS inverter of the switching output stage enables the use of minimum size devices, improving accuracy and speed in the timing of the elements. The whole circuit operates therefore on low core-supply voltage. Throughout this work, a detailed analysis carefully describes the electromagnetic structures which maximize power and efficiency of low-voltage SCPAs. Due to layout issues subsequent to limited available voltages, however, there is a practical limitation in the maximum achievable power of low-voltage SCPAs. In this work, a Multi-Port Monolithic Power Combiner (PC) is introduced to overcome this limitation and further enhance total achieved system power. The PC sums the power of a collection of SCPAs to a single output, allowing higher output powers at a high efficiency. Benefits, drawbacks and design of SCPA PCs are discussed in this work. The implemented circuit features the combination of four differential SCPAs through a four-way monolithic PC and is simulated to obtain a maximum drain efficiency of 44% at a peak output power of 29dBm on 1.1V supply voltage. Extensive spectrum analysis offers full evaluation of system performances. After exploring state-of-the-art possibilities offered by an advanced 28nm CMOS technology, this work predicts through rigorous theoretical analysis the expected evolution of SCPA performances with the scaling of CMOS Technologies. The encouraging forecast further emphasizes the importance of SCPA circuits for the future of high-performance Wireless Communications

Reconfigurable Antenna Systems: Platform implementation and low-power matters

Antennas are a necessary and often critical component of all wireless systems, of which they share the ever-increasing complexity and the challenges of present and emerging trends. 5G, massive low-orbit satellite architectures (e.g. OneWeb), industry 4.0, Internet of Things (IoT), satcom on-the-move, Advanced Driver Assistance Systems (ADAS) and Autonomous Vehicles, all call for highly flexible systems, and antenna reconfigurability is an enabling part of these advances. The terminal segment is particularly crucial in this sense, encompassing both very compact antennas or low-profile antennas, all with various adaptability/reconfigurability requirements. This thesis work has dealt with hardware implementation issues of Radio Frequency (RF) antenna reconfigurability, and in particular with low-power General Purpose Platforms (GPP); the work has encompassed Software Defined Radio (SDR) implementation, as well as embedded low-power platforms (in particular on STM32 Nucleo family of micro-controller). The hardware-software platform work has been complemented with design and fabrication of reconfigurable antennas in standard technology, and the resulting systems tested. The selected antenna technology was antenna array with continuously steerable beam, controlled by voltage-driven phase shifting circuits. Applications included notably Wireless Sensor Network (WSN) deployed in the Italian scientific mission in Antarctica, in a traffic-monitoring case study (EU H2020 project), and into an innovative Global Navigation Satellite Systems (GNSS) antenna concept (patent application submitted). The SDR implementation focused on a low-cost and low-power Software-defined radio open-source platform with IEEE 802.11 a/g/p wireless communication capability. In a second embodiment, the flexibility of the SDR paradigm has been traded off to avoid the power consumption associated to the relevant operating system. Application field of reconfigurable antenna is, however, not limited to a better management of the energy consumption. The analysis has also been extended to satellites positioning application. A novel beamforming method has presented demonstrating improvements in the quality of signals received from satellites. Regarding those who deal with positioning algorithms, this advancement help improving precision on the estimated position