A Novel Decomposition for Control of DC Circuits and Grid Models with Heterogeneous Energy Sources

The way in which electric power depends on the topology of circuits with mixed voltage and current sources is examined. The power flowing in any steady-state DC circuit is shown to depend on a minimal set of key variables called fundamental node voltages and fundamental edge currents. Every steady-state DC circuit can be decomposed into a voltage controlled subcircuit and a current controlled subcircuit. In terms of such a decomposition, the I^2R losses of a mixed source circuit are always the sum of losses on the voltage controlled subcircuit and the current controlled subcircuit. The paper concludes by showing that the total power flowing in a mixed source circuit can be found as critical points of the power expressed in terms of the key voltage and current variables mentioned above. The possible relationship to topology control of electric grid operations is discussed

Paradigm and paradox in topology control of power grids

Corrective Transmission Switching can be used by the grid operator to relieve line overloading and voltage violations, improve system reliability, and reduce system losses. Power grid optimization by means of line switching is typically formulated as a mixed integer programming problem (MIP). Such problems are known to be computationally intractable, and accordingly, a number of heuristic approaches to grid topology reconfiguration have been proposed in the power systems literature. By means of some low order examples (3-bus systems), it is shown that within a reasonably large class of “greedy” heuristics, none can be found that perform better than the others across all grid topologies. Despite this cautionary tale, statistical evidence based on a large number of simulations using IEEE 118-bus systems indicates that among three heuristics, a globally greedy heuristic is the most computationally intensive, but has the best chance of reducing generation costs while enforcing N-1 connectivity. It is argued that, among all iterative methods, the locally optimal switches at each stage have a better chance in not only approximating a global optimal solution but also greatly limiting the number of lines that are switched.First author draf

Paradigm and Paradox in Topology Control of Power Grids

Corrective Transmission Switching can be used by the grid operator to relieve line overloading and voltage violations, improve system reliability, and reduce system losses. Power grid optimization by means of line switching is typically formulated as a mixed integer programming problem (MIP). Such problems are known to be computationally intractable, and accordingly, a number of heuristic approaches to grid topology reconfiguration have been proposed in the power systems literature. By means of some low order examples (3-bus systems), it is shown that within a reasonably large class of greedy heuristics, none can be found that perform better than the others across all grid topologies. Despite this cautionary tale, statistical evidence based on a large number of simulations using using IEEE 118- bus systems indicates that among three heuristics, a globally greedy heuristic is the most computationally intensive, but has the best chance of reducing generation costs while enforcing N-1 connectivity. It is argued that, among all iterative methods, the locally optimal switches at each stage have a better chance in not only approximating a global optimal solution but also greatly limiting the number of lines that are switched

Challenges and Opportunities for Second-life Batteries: A Review of Key Technologies and Economy

Due to the increasing volume of Electric Vehicles in automotive markets and the limited lifetime of onboard lithium-ion batteries (LIBs), the large-scale retirement of LIBs is imminent. The battery packs retired from Electric Vehicles still own 70%-80% of the initial capacity, thus having the potential to be utilized in scenarios with lower energy and power requirements to maximize the value of LIBs. However, spent batteries are commonly less reliable than fresh batteries due to their degraded performance, thereby necessitating a comprehensive assessment from safety and economic perspectives before further utilization. To this end, this paper reviews the key technological and economic aspects of second-life batteries (SLBs). Firstly, we introduce various degradation models for first-life batteries and identify an opportunity to combine physics-based theories with data-driven methods to establish explainable models with physical laws that can be generalized. However, degradation models specifically tailored to SLBs are currently absent. Therefore, we analyze the applicability of existing battery degradation models developed for first-life batteries in SLB applications. Secondly, we investigate fast screening and regrouping techniques and discuss the regrouping standards for the first time to guide the classification procedure and enhance the performance and safety of SLBs. Thirdly, we scrutinize the economic analysis of SLBs and summarize the potentially profitable applications. Finally, we comprehensively examine and compare power electronics technologies that can substantially improve the performance of SLBs, including high-efficiency energy transformation technologies, active equalization technologies, and technologies to improve reliability and safety

Paradigm and paradox in power networks

Well known in the theory of network flows, Braess paradox states that adding path(s) to a congested road network may increase overall journey time. In transportation networks, the phenomenon results from selfish routing. In power systems, an analogous increase in congestion can arise as a consequence of Kirchhoff's laws, suggesting opportunities to optimize grid topology. The thesis starts with the discussion of Braess-like congestion phenomena in linear circuits. We prove that adding electrical path(s) always increases congestion in networks powered by voltage sources, while the opposite in networks driven by current sources. Although such predictability is not present in networks controlled by a mixture of voltage and current sources, our results offer a clean decomposition that completely separates the effect of current sources and voltage sources on total loss. The culmination of this research is a set of four equivalent methods of computing I^2R loss in mixed-source networks. We go on to explore network decomposition in combination with greedy sequential line switching heuristics to address the NP-hardness of power grid topology control. By means of some low order examples, it is shown that within a reasonably large class of greedy heuristics, none can be found that perform better than the others across all grid topologies. Despite this cautionary tale, statistical evidence indicates that, among three most representative heuristics, the global greedy heuristic is most computationally intensive but has the best chance of reducing generation cost while enforcing connectivity. The final part of the thesis presents a new approach to grid decomposition using vertex cut sets. We show that each vertex cut set and corresponding grid decomposition establishes a natural upper bound on the interactions between subgrids as nodal injections are regulated within each. Using such decomposition, it becomes possible to isolate congestion effects to a relatively small subgrid. A fast grid decomposition heuristic based on vertex cut sets and locational marginal prices is then proposed and studied through simulations on IEEE 118-bus system. On average, the computational cost is significantly reduced and the generation cost saving is similar to what is obtained with a global greedy algorithm

Power Grid Decomposition Based on Vertex Cut Sets and Its Applications to Topology Control and Power Trading

It is well known that the reserves/redundancies built into the transmission grid in order to address a variety of contingencies over a long planning horizon may, in the short run, cause economic dispatch inefficiency. Accordingly, power grid optimization by means of short term line switching has been proposed and is typically formulated as a mixed integer programming problem by treating the state of the transmission lines as a binary decision variable, i.e. in-service or out-of-service, in the optimal power flow problem. To handle the combinatorial explosion, a number of heuristic approaches to grid topology reconfiguration have been proposed in the literature. This paper extends our recent results on the iterative heuristics and proposes a fast grid decomposition algorithm based on vertex cut sets with the purpose of further reducing the computational cost. The paper concludes with a discussion of the possible relationship between vertex cut sets in transmission networks and power trading

Multiplex PI-Control for Consensus in Networks of Heterogeneous Linear Agents

In this paper, we propose a multiplex proportional-integral approach, for solving consensus problems in networks of heterogeneous nodes dynamics affected by constant disturbances. The proportional and integral actions are deployed on two different layers across the network, each with its own topology. Sufficient conditions for convergence are derived that depend upon the structure of the network, the parameters characterizing the control layers and the node dynamics. The effectiveness of the theoretical results is illustrated using a power network model as a representative example.Comment: 13 pages, 6 Figures, Preprint submitted to Automatic

SCALABLE INTEGRATED CIRCUIT SIMULATION ALGORITHMS FOR ENERGY-EFFICIENT TERAFLOP HETEROGENEOUS PARALLEL COMPUTING PLATFORMS

Integrated circuit technology has gone through several decades of aggressive scaling.It is increasingly challenging to analyze growing design complexity. Post-layout SPICE simulation can be computationally prohibitive due to the huge amount of parasitic elements, which can easily boost the computation and memory cost. As the decrease in device size, the circuits become more vulnerable to process variations. Designers need to statistically simulate the probability that a circuit does not meet the performance metric, which requires millions times of simulations to capture rare failure events. Recent, multiprocessors with heterogeneous architecture have emerged as mainstream computing platforms. The heterogeneous computing platform can achieve highthroughput energy efficient computing. However, the application of such platform is not trivial and needs to reinvent existing algorithms to fully utilize the computing resources. This dissertation presents several new algorithms to address those aforementioned two significant and challenging issues on the heterogeneous platform. Harmonic Balance (HB) analysis is essential for efficient verification of large postlayout RF and microwave integrated circuits (ICs). However, existing methods either suffer from excessively long simulation time and prohibitively large memory consumption or exhibit poor stability. This dissertation introduces a novel transient-simulation guided graph sparsification technique, as well as an efficient runtime performance modeling approach tailored for heterogeneous manycore CPU-GPU computing system to build nearly-optimal subgraph preconditioners that can lead to minimum HB simulation runtime. Additionally, we propose a novel heterogeneous parallel sparse block matrix algorithm by taking advantages of the structure of HB Jacobian matrices as well as GPU’s streaming multiprocessors to achieve optimal workload balancing during the preconditioning phase of HB analysis. We also show how the proposed preconditioned iterative algorithm can efficiently adapt to heterogeneous computing systems with different CPU and GPU computing capabilities. Extensive experimental results show that our HB solver can achieve up to 20X speedups and 5X memory reduction when compared with the state-of-the-art direct solver highly optimized for twelve-core CPUs. In nowadays variation-aware IC designs, cell characterizations and SRAM memory yield analysis require many thousands or even millions of repeated SPICE simulations for relatively small nonlinear circuits. In this dissertation, for the first time, we present a massively parallel SPICE simulator on GPU, TinySPICE, for efficiently analyzing small nonlinear circuits. TinySPICE integrates a highly-optimized shared-memory based matrix solver and fast parametric three-dimensional (3D) LUTs based device evaluation method. A novel circuit clustering method is also proposed to improve the stability and efficiency of the matrix solver. Compared with CPU-based SPICE simulator, TinySPICE achieves up to 264X speedups for parametric SRAM yield analysis without loss of accuracy