Topology-Transparent Scheduling in Mobile Ad Hoc Networks With Multiple Packet Reception Capability

Recent advances in the physical layer have enabled wireless devices to have multiple packet reception (MPR) capability, which is the capability of decoding more than one packet, simultaneously, when concurrent transmissions occur. In this paper, we focus on the interaction between the MPR physical layer and the medium access control (MAC) layer. Some random access MAC protocols have been proposed to improve the network performance by exploiting the powerful MPR capability. However, there are very few investigations on the schedule-based MAC protocols. We propose a novel m-MPR-l-code topology-transparent scheduling ((m, l)-TTS) algorithm for mobile ad hoc networks with MPR, where m indicates the maximum number of concurrent transmissions being decoded, and l is the number of codes assigned to each user. Our algorithm can take full advantage of the MPR capability to improve the network performance. The minimum guaranteed throughput and average throughput of our algorithm are studied analytically. The improvement of our (m, l)-TTS algorithm over the conventional topology-transparent scheduling algorithms with the collision-based reception model is linear with m. The simulation results show that our proposed algorithm performs better than slotted ALOHA as well.published_or_final_versio

Robust Multidimentional Chinese Remainder Theorem for Integer Vector Reconstruction

The problem of robustly reconstructing an integer vector from its erroneous remainders appears in many applications in the field of multidimensional (MD) signal processing. To address this problem, a robust MD Chinese remainder theorem (CRT) was recently proposed for a special class of moduli, where the remaining integer matrices left-divided by a greatest common left divisor (gcld) of all the moduli are pairwise commutative and coprime. The strict constraint on the moduli limits the usefulness of the robust MD-CRT in practice. In this paper, we investigate the robust MD-CRT for a general set of moduli. We first introduce a necessary and sufficient condition on the difference between paired remainder errors, followed by a simple sufficient condition on the remainder error bound, for the robust MD-CRT for general moduli, where the conditions are associated with (the minimum distances of) these lattices generated by gcld's of paired moduli, and a closed-form reconstruction algorithm is presented. We then generalize the above results of the robust MD-CRT from integer vectors/matrices to real ones. Finally, we validate the robust MD-CRT for general moduli by employing numerical simulations, and apply it to MD sinusoidal frequency estimation based on multiple sub-Nyquist samplers.Comment: 12 pages, 5 figur

Algorithms and VLSI architectures for parametric additive synthesis

A parametric additive synthesis approach to sound synthesis is advantageous as it can model sounds in a large scale manner, unlike the classical sinusoidal additive based synthesis paradigms. It is known that a large body of naturally occurring sounds are resonant in character and thus fit the concept well. This thesis is concerned with the computational optimisation of a super class of form ant synthesis which extends the sinusoidal parameters with a spread parameter known as band width. Here a modified formant algorithm is introduced which can be traced back to work done at IRCAM, Paris. When impulse driven, a filter based approach to modelling a formant limits the computational work-load. It is assumed that the filter's coefficients are fixed at initialisation, thus avoiding interpolation which can cause the filter to become chaotic. A filter which is more complex than a second order section is required. Temporal resolution of an impulse generator is achieved by using a two stage polyphase decimator which drives many filterbanks. Each filterbank describes one formant and is composed of sub-elements which allow variation of the formant’s parameters. A resource manager is discussed to overcome the possibility of all sub- banks operating in unison. All filterbanks for one voice are connected in series to the impulse generator and their outputs are summed and scaled accordingly. An explorative study of number systems for DSP algorithms and their architectures is investigated. I invented a new theoretical mechanism for multi-level logic based DSP. Its aims are to reduce the number of transistors and to increase their functionality. A review of synthesis algorithms and VLSI architectures are discussed in a case study between a filter based bit-serial and a CORDIC based sinusoidal generator. They are both of similar size, but the latter is always guaranteed to be stable