Phased burst error-correcting array codes

Various aspects of single-phased burst-error-correcting array codes are explored. These codes are composed of two-dimensional arrays with row and column parities with a diagonally cyclic readout order; they are capable of correcting a single burst error along one diagonal. Optimal codeword sizes are found to have dimensions n1×n2 such that n2 is the smallest prime number larger than n1. These codes are capable of reaching the Singleton bound. A new type of error, approximate errors, is defined; in q-ary applications, these errors cause data to be slightly corrupted and therefore still close to the true data level. Phased burst array codes can be tailored to correct these codes with even higher rates than befor

A decoding procedure for the Reed-Solomon codes

A decoding procedure is described for the (n,k) t-error-correcting Reed-Solomon (RS) code, and an implementation of the (31,15) RS code for the I4-TENEX central system. This code can be used for error correction in large archival memory systems. The principal features of the decoder are a Galois field arithmetic unit implemented by microprogramming a microprocessor, and syndrome calculation by using the g(x) encoding shift register. Complete decoding of the (31,15) code is expected to take less than 500 microsecs. The syndrome calculation is performed by hardware using the encoding shift register and a modified Chien search. The error location polynomial is computed by using Lin's table, which is an interpretation of Berlekamp's iterative algorithm. The error location numbers are calculated by using the Chien search. Finally, the error values are computed by using Forney's method

Decoding of Repeated-Root Cyclic Codes up to New Bounds on Their Minimum Distance

The well-known approach of Bose, Ray-Chaudhuri and Hocquenghem and its generalization by Hartmann and Tzeng are lower bounds on the minimum distance of simple-root cyclic codes. We generalize these two bounds to the case of repeated-root cyclic codes and present a syndrome-based burst error decoding algorithm with guaranteed decoding radius based on an associated folded cyclic code. Furthermore, we present a third technique for bounding the minimum Hamming distance based on the embedding of a given repeated-root cyclic code into a repeated-root cyclic product code. A second quadratic-time probabilistic burst error decoding procedure based on the third bound is outlined. Index Terms Bound on the minimum distance, burst error, efficient decoding, folded code, repeated-root cyclic code, repeated-root cyclic product cod

Error control for reliable digital data transmission and storage systems

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this paper we present some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative alorithm to find the error locator polynomial. Two codes are considered: (1) a d sub min = 4 single-byte-error-correcting (SBEC), double-byte-error-detecting (DBED) RS code; and (2) a d sub min = 6 double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS code

Iterative joint channel and data estimation for rank-deficient MIMO-OFDM

In this paper we propose a turbo-detected multi-antenna-multi-carrier receiver scheme. Following the philosophy of the turbo processing, our turbo MIMO-OFDM receiver comprises a succession of detection modules, namely the channel estimator, the space-time detector and the decoder, which iteratively exchange soft bit-related information and thus facilitate a substantial improvement of the overall system performance. In this paper we analyze the achievable performance of the iterative system proposed with the aim of documenting the various design trade-offs, such as the achievable error-rate performance, the attainable data-rate as well as the associated computational complexity. Specifically, we report a virtually error-free performance for a rate-1/2 turbo-coded 8x8-QPSK-OFDM system, exhibiting an effective throughput of 8*2/2=8 bits/sec/Hz and having a pilot overhead of only 10%, at SNR of 7.5dB and normalized Doppler frequency of 0.003, which corresponds to a mobile terminal speed of about 65 km/h

A B-ISDN-compatible modem/codec

Coded modulation techniques for development of a broadband integrated services digital network (B-ISDN)-compatible modem/codec are investigated. The selected baseband processor system must support transmission of 155.52 Mbit/s of data over an INTELSAT 72-MHz transponder. Performance objectives and fundamental system parameters, including channel symbol rate, code rate, and the modulation scheme are determined. From several candidate codes, a concatenated coding system consisting of a coded octal phase shift keying modulation as the inner code and a high rate Reed-Solomon as the outer code is selected and its bit error rate performance is analyzed by computer simulation. The hardware implementation of the decoder for the selected code is also described

EVENODD: An Efficient Scheme for Tolerating Double Disk Failures in RAID Architectures

We present a novel method, that we call EVENODD, for tolerating up to two disk failures in RAID architectures. EVENODD employs the addition of only two redundant disks and consists of simple exclusive-OR computations. This redundant storage is optimal, in the sense that two failed disks cannot be retrieved with less than two redundant disks. A major advantage of EVENODD is that it only requires parity hardware, which is typically present in standard RAID-5 controllers. Hence, EVENODD can be implemented on standard RAID-5 controllers without any hardware changes. The most commonly used scheme that employes optimal redundant storage (i.e., two extra disks) is based on Reed-Solomon (RS) error-correcting codes. This scheme requires computation over finite fields and results in a more complex implementation. For example, we show that the complexity of implementing EVENODD in a disk array with 15 disks is about 50% of the one required when using the RS scheme. The new scheme is not limited to RAID architectures: it can be used in any system requiring large symbols and relatively short codes, for instance, in multitrack magnetic recording. To this end, we also present a decoding algorithm for one column (track) in error