Trade-Off Approach for GHASH Computation Based on a Block-Merging Strategy

In the Galois counter mode (GCM) of encryption an authentication tag is computed with a sequence of multiplications and additions in F 2 m. In this paper we focus on multiply-and-add architecture with a suquadratic space complexity multiplier in F 2 m. We propose a recom-bination of the architecture of P. Patel (Master Thesis, U. Waterloo, ON. Canada, 2008) which is based on a subquadratic space complexity Toeplitz matrix vector product. We merge some blocks of the recombined architecture in order to reduce the critical path delay. We obtain an architecture with a subquadratic space complexity of O(log 2 (m)m log 2 (m)) and a reduced delay of (1.59 log 2 (m) + log 2 (δ))D X + D A where δ is a small constant. To the best of our knowledge, this is the first multiply-and-add architecture with subquadratic space complexity and delay smaller than 2 log 2 (m)D X

Overlap-free Karatsuba-Ofman Polynomial Multiplication Algorithms

We describe how a simple way to split input operands allows for fast VLSI implementations of subquadratic $GF(2)[x]$ Karatsuba-Ofman multipliers. The theoretical XOR gate delay of the resulting multipliers is reduced significantly. For example, it is reduced by about 33\% and 25\% for $n=2^{t}$ and $n=3^{t}$ $(t>1)$, respectively. To the best of our knowledge, this parameter has never been improved since the original Karatsuba-Ofman algorithm was first used to design $GF(2^n)$ multipliers in 1990

Toeplitz matrix-vector product based GF(2^n) shifted polynomial basis multipliers for all irreducible pentanomials

Besides Karatsuba algorithm, optimal Toeplitz matrix-vector product (TMVP) formulae is another approach to design GF(2^n) subquadratic multipliers. However, when GF(2^n) elements are represented using a shifted polynomial basis, this approach is currently appliable only to GF(2^n)s generated by all irreducible trinomials and a special type of irreducible pentanomials, not all general irreducible pentanomials. The reason is that no transformation matrix, which transforms the Mastrovito matrix into a Toeplitz matrix, has been found. In this article, we propose such a transformation matrix and its inverse matrix for an arbitrary irreducible pentanomial. Because there is no known value of n for which either an irreducible trinomial or an irreducible pentanomial does not exist, this transformation matrix makes the TMVP approach a universal tool, i.e., it is applicable to all practical GF(2^n)s

(127, k, d) Reed-Solomon code with erasures: simulation and field programmable gate arrays (FPGA) design

Telecommunication applications require transmitting data with different format such as sound, video, email, measures, signalling and help contents . This leads to a growing complexity of transmitting systems and to higher and higher data rates . On reception, the system must be able to quickly detect and correct errors due to the transmission channel noise (decreasing error rate) . Error detecting-correcting codes suited to applications reduce the error rate (cyclic codes, convolutional code . . .) . This paper presents an overview of the implementation of a (127, k, d) Reed-Solomon error-correcting code with erasures . The technology used to mark on symbols is described in details here . The coding algorithm computes the codewords and marks the symbols . The decoding algorithm detects and corrects either the errors t' = t, or the erasures e' = 2* t, or a combination of the two (e' + 2 * t' < d-1). The error detection is possible for a number of erasures exceeding 2 * t . The number of rectifiable errors is t . This work is the result of the collaboration between the LICM laboratory and TDF-C2R company . Many Hamming distances of a (127, k, d) Reed-Solomon error-correcting code with erasure have been tested with measure files, simulating different real environments . Results obtained from computer simulations using diversified environment models are in good agreement with analytical results . Moreover, the core of the «(127, 121, 7) Reed-Solomon code with erasures» coder/decoder has been implemented on an ALTERA/FLEX1 OK family FPGA from a VHDL specification . This core can be used to design applications with continuous data streams .Les applications actuelles de télécommunications nécessitent la transmission de données aussi diverses que le son, la vidéo, la messagerie et les données de mesures, de signalisations et d'assistance. Cela entraîne une complexité croissante des systèmes de transmission et un débit de plus en plus élevé. A la réception, le système doit pouvoir détecter et corriger rapidement les éventuelles erreurs dues au bruit de canal (diminution du taux d'erreurs). Une des techniques pour diminuer ce taux est d'utiliser un code détecteur correcteur d'erreurs adapté à l'application (codes cycliques, code convolutif, .,). Plus spécifiquement, cet article concerne un code détecteur correcteur d'erreurs Reed-Solomon (127, k, d) avec la description complète d'une technique de marquage des symboles pour la mise en oeuvre des effacements. L'algorithme de codage calcule les mots de code et marque les symboles. L'algorithme de décodage opère soit sur les erreurs t' = t, soit sur les effacements e' = 2 * t, soit sur un panachage des deux (e' + 2 * t' ≤ d-1), t étant le nombre maximum d'erreurs corrigibles. En plus la détection des erreurs est possible pour un nombre d'effacements supérieur à 2 * t. Dans le cadre d'une étude menée conjointement entre le laboratoire LICM et TDF-C2R, plusieurs distances Hamming du code Reed-Solomon (127, k, d) ont été simulées (entre autres à partir de mesures réelles). Les résultats de simulation permettent de quantifier la valeur ajoutée concernant les effacements. De plus, la conception sur FPGA d'un code de Reed-Solomon (127, 121, 7) est étudiée afin d'implanter une fonction « codeur/décodeur avec effacements », pouvant être réutilisée lors de la synthèse d'autres applications traitant des flots de données en continu

A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design

With the continually growing use of portable computing devices and increasingly complex software applications, there is a constant push for low power high speed circuitry to support this technology. Because of the high usage and large complex circuitry required to carry out arithmetic operations used in applications such as digital signal processing, there has been a great focus on increasing the efficiency of computer arithmetic circuitry. A key player in the realm of computer arithmetic is the digital multiplier and because of its size and power consumption, it has moved to the forefront of today\u27s research. A digital reconfigurable multiplier architecture will be introduced. Regulated by a 2-bit control signal, the multiplier is capable of double and single precision multiplication, as well as fault tolerant and dual throughput single precision execution. The architecture proposed in this thesis is centered on a recursive multiplication algorithm, where a large multiplication is carried out using recursions of simpler submultiplier modules. Within each sub-multiplier module, instead of carry save adder arrays, 4:2 compressor rows are utilized for partial product reduction, which present greater efficiency, thus result in lower delay and power consumption of the whole multiplier. In addition, a study of various digital logic circuit styles are initially presented, and then three different designs of 4:2 compressor in Domino Logic are presented and simulation results confirm the property of proposed design in terms of delay, power consumption and operation frequenc

A new approach in building parallel finite field multipliers

A new method for building bit-parallel polynomial basis finite field multipliers is proposed in this thesis. Among the different approaches to build such multipliers, Mastrovito multipliers based on a trinomial, an all-one-polynomial, or an equally-spacedpolynomial have the lowest complexities. The next best in this category is a conventional multiplier based on a pentanomial. Any newly presented method should have complexity results which are at least better than those of a pentanomial based multiplier. By applying our method to certain classes of finite fields we have gained a space complexity as n2 + H - 4 and a time complexity as TA + ([ log2(n-l) ]+3)rx which are better than the lowest space and time complexities of a pentanomial based multiplier found in literature. Therefore this multiplier can serve as an alternative in those finite fields in which no trinomial, all-one-polynomial or equally-spaced-polynomial exists

Bit-parallel word-serial polynomial basis finite field multiplier in GF(2(233)).

Smart card gains extensive uses as a cryptographic hardware in security applications in daily life. The characteristics of smart card require that the cryptographic hardware inside the smart card have the trade-off between area and speed. There are two main public key cryptosystems, these are RSA cryptosystem and elliptic curve (EC) cryptosystem. EC has many advantages compared with RSA such as shorter key length and more suitable for VLSI implementation. Such advantages make EC an ideal candidate for smart card. Finite field multiplier is the key component in EC hardware. In this thesis, bit-parallel word-serial (BPWS) polynomial basis (PB) finite field multipliers are designed. Such architectures trade-off area with speed and are very useful for smart card. An ASIC chip which can perform finite field multiplication and finite field squaring using the BPWS PB finite field multiplier is designed in this thesis. The proposed circuit has been implemented using TSMC 0.18 CMOS technology. A novel 8 x 233 bit-parallel partial product generator is also designed. This new partial product generator has low circuit complexity. The design algorithm can be easily extended to w x m bit-parallel partial product generator for GF(2m).Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .T36. Source: Masters Abstracts International, Volume: 43-01, page: 0286. Advisers: H. Wu; M. Ahmadi. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004