Multivariate modelling of long memory processes with common components

In the paper a new approach to the modelling of common components in long memory processes is introduced. The approach is based on a two-step procedure relying on Fourier transform methods (firrst step) and principal components analysis (second step), which, differently from previous contributions to the literature, allows the modelling of large data sets, both in terms of temporal and cross-sectional dimensions. Monte Carlo evidence, supporting the two-step stimation procedure, is also provided, as well as an empirical application to real data.long memory; common long memory factor model; permanent-persistent-non persistent decomposition; permanent-transitory decomposition.

XMem++: Production-level Video Segmentation From Few Annotated Frames

Despite advancements in user-guided video segmentation, extracting complex objects consistently for highly complex scenes is still a labor-intensive task, especially for production. It is not uncommon that a majority of frames need to be annotated. We introduce a novel semi-supervised video object segmentation (SSVOS) model, XMem++, that improves existing memory-based models, with a permanent memory module. Most existing methods focus on single frame annotations, while our approach can effectively handle multiple user-selected frames with varying appearances of the same object or region. Our method can extract highly consistent results while keeping the required number of frame annotations low. We further introduce an iterative and attention-based frame suggestion mechanism, which computes the next best frame for annotation. Our method is real-time and does not require retraining after each user input. We also introduce a new dataset, PUMaVOS, which covers new challenging use cases not found in previous benchmarks. We demonstrate SOTA performance on challenging (partial and multi-class) segmentation scenarios as well as long videos, while ensuring significantly fewer frame annotations than any existing method. Project page: https://max810.github.io/xmem2-project-page/Comment: Accepted to ICCV 2023. 18 pages, 16 figure

Simultaneous use of shape memory alloys and permanent magnets in multistable smart structures for morphing aircraft applications

This Thesis considers the simultaneous use of shape memory alloys and permanent magnets for achieving multistable smart structures aiming towards morphing applications. Motivation for this approach lies in the poor energetic efficiency of shape memory alloys, which can void system-level benefits provided by morphing technologies. Multistability can therefore be adopted to prevent continuous operation of shape memory alloy actuators. Objectives of the study involve the combination of shape memory alloys and permanent magnets in new geometrical arrangements to achieve multistable behavior; the development of a numerical modeling procedure that is able to simulate the multi-physics nature of the studied systems; and the proposal of a geometric arrangement for morphing applications that is based on a repeating pattern of unit cells which incorporate the combined use of shape memory alloy wires and permanent magnets for multistability. The proposed modeling strategy considers a geometrically nonlinear beam finite element; a thermo-mechanical constitutive behavior for shapememoryalloys;theinteractionofcuboidalpermanentmagnetswitharbitraryorienta- tions; and node-to-element contact. Experiments are performed with three distinct systems, including a proof-of-concept beam, a three cell morphing beam metastructure, and a morphing airfoil prototype with six unit cells. Results show that the combination of shape memory alloys and permanent magnets indeed allows for multistable behavior. Furthermore, the dis- tributedactuationcapabilitiesofthe morphingmetastructureallowforsmoothandlocalized geometrical shape changes.CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível SuperiorCNPq - Conselho Nacional de Desenvolvimento Científico e TecnológicoTese (Doutorado)Esta Tese considera o uso simultâneo de ligas com memória de forma e ímãs permanentes para a obtenção de estruturas inteligentes multiestáveis, com vistas a sua aplicação em aeronaves de geometria variável. A motivação para tal abordagem reside na baixa eficiência energética associada às ligas com memória de forma, a qual pode eliminar benefícios oriundos de tecnologias relacionadas a geometria variável. Multiestabilidade pode, desta forma, ser adotada para prevenir operação contínua de atuadores baseados em ligas com memória de forma. Objetivos do estudo envolvem a combinação de ligas com memória de forma e ímãs permanentes em novos arranjos geométricos para a obtenção de comportamento multiestável; o desenvolvimento de um procedimento de modelagem numérica que pode simular a natureza multifísica dos sistemas estudados; e a proposição de um arranjo geométrico para aplicações que envolvem geometria variável, o qual é baseado num padrão repetitivo de células unitárias que incorporam o uso combinado de ligas com memória de forma e ímãs permanentes para mul- tiestabilidade. A estratégia de modelagem proposta considera um elemento finito de viga com não-linearidades geométricas; um modelo constitutivo termomecânico para ligas com memória de forma; a interação entre ímãs permanentes cúbicos com orientação arbitrária; e contato entre elemento-e-nó no contexto de elementos finitos. Experimentos são realizados com três sistemas distintos, incluindo uma viga para prova de conceito, uma metaestrutura do tipo viga com geometria variável composta por três células unitárias, e um protótipo de aerofólio com geometria variável composto por seis células unitárias. Resultados mostram que a combinação de ligas com memória de forma e ímãs permanentes permite a obtenção de comportamento multiestável. Além disso, a característica de atuação distribuída das metaestruturas com geometria variável permite alterações de forma suaves e localizadas

Testing Embedded Memories in Telecommunication Systems

Extensive system testing is mandatory nowadays to achieve high product quality. Telecommunication systems are particularly sensitive to such a requirement; to maintain market competitiveness, manufacturers need to combine reduced costs, shorter life cycles, advanced technologies, and high quality. Moreover, strict reliability constraints usually impose very low fault latencies and a high degree of fault detection for both permanent and transient faults. This article analyzes major problems related to testing complex telecommunication systems, with particular emphasis on their memory modules, often so critical from the reliability point of view. In particular, advanced BIST-based solutions are analyzed, and two significant industrial case studies presente

Microprocessor fault-tolerance via on-the-fly partial reconfiguration

This paper presents a novel approach to exploit FPGA dynamic partial reconfiguration to improve the fault tolerance of complex microprocessor-based systems, with no need to statically reserve area to host redundant components. The proposed method not only improves the survivability of the system by allowing the online replacement of defective key parts of the processor, but also provides performance graceful degradation by executing in software the tasks that were executed in hardware before a fault and the subsequent reconfiguration happened. The advantage of the proposed approach is that thanks to a hardware hypervisor, the CPU is totally unaware of the reconfiguration happening in real-time, and there's no dependency on the CPU to perform it. As proof of concept a design using this idea has been developed, using the LEON3 open-source processor, synthesized on a Virtex 4 FPG

EDACs and test integration strategies for NAND flash memories

Mission-critical applications usually presents several critical issues: the required level of dependability of the whole mission always implies to address different and contrasting dimensions and to evaluate the tradeoffs among them. A mass-memory device is always needed in all mission-critical applications: NAND flash-memories could be used for this goal. Error Detection And Correction (EDAC) techniques are needed to improve dependability of flash-memory devices. However also testing strategies need to be explored in order to provide highly dependable systems. Integrating these two main aspects results in providing a fault-tolerant mass-memory device, but no systematic approach has so far been proposed to consider them as a whole. As a consequence a novel strategy integrating a particular code-based design environment with newly selected testing strategies is presented in this pape

Online and Offline BIST in IP-Core Design

This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraint

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints