Reconocimiento de caracteres por medio de una red neuronal artificial

En este trabajo se presenta la implementación de un sistema de reconocimientode caracteres en una tarjeta de desarrollo FPGA de propósito general. La clasificación de los caracteres se realiza por medio de un modelo de red neuronal conocido como Feed-forward backpropagation. Se utiliza la herramienta de redes neuronales NNTool de Matlab, para crear, entrenar y simular este tipo de Red Neuronal Artificial (RNA) con cinco diferentes patrones de entrenamiento. Para realizar la implementación, estas RNAs, son traducidas del modelo computacional a un modelo realizable en hardware, el cual es descrito mediante bloques en Matlab/Simulink y Xilinx System Generator (XSG). El archivo de configuración bitstream, necesario para la programación del FPGA, es generado por XSG para posteriormente ser implementado con Xilinx ISE foundation en la FPGA.Palabras Clave: FPGA, Matlab / Simulink, reconocimiento de caracteres, red neuronal artificial, Xilinx System Generator.

Intrinsically Evolvable Artificial Neural Networks

Dedicated hardware implementations of neural networks promise to provide faster, lower power operation when compared to software implementations executing on processors. Unfortunately, most custom hardware implementations do not support intrinsic training of these networks on-chip. The training is typically done using offline software simulations and the obtained network is synthesized and targeted to the hardware offline. The FPGA design presented here facilitates on-chip intrinsic training of artificial neural networks. Block-based neural networks (BbNN), the type of artificial neural networks implemented here, are grid-based networks neuron blocks. These networks are trained using genetic algorithms to simultaneously optimize the network structure and the internal synaptic parameters. The design supports online structure and parameter updates, and is an intrinsically evolvable BbNN platform supporting functional-level hardware evolution. Functional-level evolvable hardware (EHW) uses evolutionary algorithms to evolve interconnections and internal parameters of functional modules in reconfigurable computing systems such as FPGAs. Functional modules can be any hardware modules such as multipliers, adders, and trigonometric functions. In the implementation presented, the functional module is a neuron block. The designed platform is suitable for applications in dynamic environments, and can be adapted and retrained online. The online training capability has been demonstrated using a case study. A performance characterization model for RC implementations of BbNNs has also been presented