Signal processing using short word-length

Recently short word-length (normally 1 bit or bits) processing has become a promising technique. However, there are unresolved issues in sigma-delta modulation, which is the basis for 1b/2b systems. These issues hindered the full adoption of single-bit techniues in industry. Among these problems is the stability of high-order modulators and the limit cycle behaviour. More importantly, there is no adaptive LMS structure of any kind in 1b/2b domain. The challenge in this problem is the harsh quantization that prevents straightforward LMS application. In this thesis, the focus has been made on three axes: designing new single-bit DSP applications, proposing novel approaches for stability analysis, and tacking the unresolved problems of 1b/2b adaptive filtering. Two structures for 1b digital comb filtering are proposed. A ternary DC blocker structure is also presented and performanc e is tested. We also proposed a single-bit multiplierless DC-blocking structure. The stability of a single-bit high-order signma-delta modulator is studied under dc inputs. A new approach for stability analysis is proposed based on analogy with PLL analysis. Finally we succeeded in designing 1b/2b Wiener-like filtering and introduced (for the first time) three 1b/2b adaptive schemes

Design and analysis of short word length DSP systems for mobile communication

Recently, many general purpose DSP applications such as Least Mean Squares-Like single-bit adaptive filter algorithms have been developed using the Short Word Length (SWL) technique and have been shown to achieve similar performance as multi-bit systems. A key function in SWL systems is sigma delta modulation (ΣΔM) that operates at an over sampling ratio (OSR), in contrast to the Nyquist rate sampling typically used in conventional multi-bit systems. To date, the analysis of SWL (or single-bit) DSP systems has tended to be performed using high-level tools such as MATLAB, with little work reported relating to their hardware implementation, particularly in Field Programmable Gate Arrays (FPGAs). This thesis explores the hardware implementation of single-bit systems in FPGA using the design and implementation in VHDL of a single-bit ternary FIR-like filter as an illustrative example. The impact of varying OSR and bit-width of the SWL filter has been determined, and a comparison undertaken between the area-performance-power characteristics of the SWL FIR filter compared to its equivalent multi-bit filter. In these experiments, it was found that single-bit FIR-like filter consistently outperforms the multi-bit technique in terms of its area, performance and power except at the highest filter orders analysed in this work. At higher orders, the ΣΔ approach retains its power and performance advantages but exhibits slightly higher chip area. In the second stage of thesis, three encoding techniques called canonical signed digit (CSD), 2’s complement, and Redundant Binary Signed Digit (RBSD) were designed and investigated on the basis of area-performance in FPGA at varying OSR. Simulation results show that CSD encoding technique does not offer any significant improvement as compared to 2’s complement as in multi-bit domain. Whereas, RBSD occupies double the chip area than other two techniques and has poor performance. The stability of the single-bit FIR-like filter mainly depends upon IIR remodulator due to its recursive nature. Thus, we have investigated the stability IIR remodulator and propose a new model using linear analysis and root locus approach that takes into account the widely accepted second order sigma-delta modulator state variable upper bounds. Using proposed model we have found new feedback parameters limits that is a key parameter in single-bit IIR remodulator stability analysis. Further, an analysis of single-bit adaptive channel equalization in MATLAB has been performed, which is intended to support the design and development of efficient algorithm for single-bit channel equalization. A new mathematical model has been derived with all inputs, coefficients and outputs in single-bit domain. The model was simulated using narrowband signals in MATLAB and investigated on the basis of symbol error rate (SER), signal-to-noise ratio (SNR) and minimum mean squared error (MMSE). The results indicate that single-bit adaptive channel equalization is achievable with narrowband signals but that the harsh quantization noise has great impact in the convergence

A multiplierless DC-blocker for single-bit sigma-delta modulated signals

The DC content in single-bit domain is both undesirable and hard to remove. In this paper we propose a single-bit multiplierless DC-blocker structure. The input is assumed to be sigma-delta modulated bitstream. This DC-blocker is designed using a delta modulator topology with a sigma-delta modulator (SDM) embedded in its feedback path. Its performance is investigated in terms of the overall signal-to-noise ratio, the effectiveness of DC removal, and the stability. The proposed structure is efficient for hardware realisation