Using statistical metrology to understand pattern-dependent ILD thickness variation in oxide CMP processes

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (leaves 46-47).by Rajesh Ramji Divecha.M.Eng

Growth and Characterisation of Low-k dielectric Spin on Glass [QC585. A963 2002 f rb] [Microfiche 7021]

Dimensi didalam peranti mickro VLSI semakin berkurangan dengan satu objektif, iaitu untuk meningkatkan laju pengendalian. Device dimension in VLSI circuit constantly shrink with one main objective, i.e. increase in speed

Dielectric characteristics of spin-coated dielectric films using on-wafer parallel-plate capacitors at microwave frequencies

Includes bibliographical references.Dielectric properties of spin-coated dielectric insulators suitable for high-speed device fabrication are investigated. Complex dielectric permittivities and tangential losses of two polyimides, bisbenzocyclobutene (BCB), and a spin-on-glass (SOG) were extracted from the measured microwave reflection coefficient, S11, of parallel-plate capacitors over a frequency range of 50 MHz to 40 GHz. A model for the dielectric permittivity as a function of frequency is developed based on measured data with a minimum square error of less than 10-4 between measured and modeled microwave reflection coefficients. A circuit model for the pad capacitance is obtained based on geometrical and physical considerations. The relationship between the dielectric loss and its thickness is considered. Experimental results are fitted to Debye and Cole-Cole models.This work has been supported in part by the Defense Advanced Research Projects Agency under contract number DAAD19-03-1-0059 and by Yarmouk University in Irbid, Jordan

The study of advanced materials using neutrons

The first part of this thesis describes a new methodology based on a novel combination of x-ray reflectivity and small-angle neutron scattering to evaluate the structural properties of porous silica thin films about one micrometer thick supported on silicon wafer substrates. To complement these results, film composition was determined by high-energy ion scattering techniques. For the sample thin film presented here, the overall film density was found to be (0.55 ± 0.01) g/cm3 with a pore wall density of (1.16 ± 0.05) g/cm3 and a porosity of (53 ± 1) %. The average dimension for the pores was found to be (65 ± 1) Å. It was determined that (22.1 ± 0.5) % of the pores had connective paths to the free surface. The mass fraction of water absorption was (3.0 ± 0.5) % and the coefficient of thermal expansion was (60 ± 20) x 10-6/°C from room temperature to 175 °C. In the second part of this thesis, we elucidate the structure of a small molecule liquid crystal/polymer interface using specular neutron reflectivity. More specifically, we examined the interfacial transition zone width of a small molecule liquid crystal/polymer interface as a function of increasing temperature. We found that the interface between a thin film (≈ 1000 Å thick) of the liquid crystal 4\u27-n-octyl-4-cyanobiphenyl (8CB) and a thin film (≈ 800 Å thick) of deuterated poly(methyl methacrylate) (d-PMMA) is broad and broadens with increasing temperature. It is also observed that the thin film geometry influences the mixing behavior of the PMMA/8CB system. These results may have implications on current theories of liquid crystal display devices that are formed by the phase separation of liquid crystal polymer mixtures

Low Temperature RF MEMS Inductors Using Porous Anodic Alumina

In today’s communication devices, the need for high performance inductors is increasing as they are extensively used in RF integrated circuits (RFICs). This need is even more pronounced for variable inductors as they are widely required in tunable filters, voltage controlled amplifiers (VCO) and low noise amplifiers (LNA). For RFICs, the main tuning elements are solid state varactors that are used in conjunction with invariable inductors. However, they have limited linearity, high resistive losses, and low self resonant frequencies. This emphasizes the need for developing another tuning element that can be fabricated monolithically with ICs and can offer high range of tuning. Due to the ease of CMOS integration and low cost silicon based IC fabrication, the inductors currently used are a major source of energy loss, therefore driving the overall quality factor and performance of the chip down. During the last decade there has been an increase in research in RF MicroelectroMechanical Systems (RF MEMS) to develop high quality on chip tunable RF components. MEMS capacitors were initially proposed to substitute the existing varactors, however they can not be easily integrated on top of CMOS circuits. RF MEMS variable inductors have recently attracted attention as a better alternative. The research presented here explores using porous anodic alumina (PAA) in CMOS and MEMS fabrication. Due to its low cost and low temperature processing, PAA is an excellent candidate for silicon system integration. At first, PAA is explored as an isolation layer between the inductor and the lossy silicon substrate. Simulations show that although the dielectric constant of the PAA is tunable, the stress produced by the required thicker layers is problematic. Nevertheless, the use of PAA as a MEMS material shows much more promise. Tunable RF MEMS inductors based on bimorph sandwich layer of aluminum PAA and aluminum are fabricated and tested. A tuning range of 31% is achieved for an inductance variation of 5.8 nH to 7.6 nH at 3 GHz. To further improve the Q, bimorph layers of gold and PAA are fabricated on Alumina substrates. A lower tuning range is produced; however the quality factor performance is greatly improved. A peak Q of over 30 with a demonstrated 3% tuning range is presented. Depending on the need for either high performance or tunability, two types of tunable RF MEMS inductors are presented. Although PAA shows promise as a mechanical material for MEMS, the processing parameters (mainly stress and loss tangent) need to be improved if used as an isolation layer. To our knowledge, this is the first time this material has been proposed and successfully used as a structural material for MEMS devices and CMOS processes

Through-substrate interconnects for 3-D integration and RF systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.Includes bibliographical references (p. 123-132).Interconnects on silicon chips are fabricated on the top surface with an ever-increasing number of metal layers necessary to just meet performance needs. While devices have scaled according to Moore's law, interconnects have lagged. As metal line widths shrink and line lengths increase, parasitic resistance, capacitance, and inductance degrade circuit performance by increasing delays, loading, and power consumption. Separately, silicon has been supplanting GaAs in low-end, consumer RF applications. Improving the high-frequency performance of silicon by reducing ground inductance will project silicon technology into high-end RF and mm-wave applications. Furthermore, silicon-based systems allow for integration with digital blocks for system-on-chip (SoC). However, this introduces digital noise into the substrate, which interferes with the operation of RF/analog circuits. To address these challenges, we have developed a low-impedance, high-aspect ratio, through-substrate interconnect technology in silicon. Through-substrate vias exploit the third dimension by connecting the front to the backside of a chip so that power, ground, and global signals can be routed on the backside. Substrate vias can also be used to connect chip stacks in system-in-package designs.(cont.) They also provide a low-inductance ground for RFICs and enable a novel way to reduce substrate noise for SoC. The fabrication process features backside patterning for routing of different signals on the back of the chip. Fabricated through-substrate vias were fully characterized using S parameters measured up to 50 GHz. The via resistance, inductance, and sidewall capacitance were extracted from these measurements. We report record-low inductance for high-aspect ratio vias, via resistance less than 1 R, and sidewall capacitance that approaches theory. We have also examined the application of substrate vias arranged as a Faraday cage to reduce substrate noise for SoC. The Faraday cage is exceptional in suppressing substrate crosstalk, especially at high frequencies: 32 dB better than the reference at 10 GHz, and 26 dB at 50 GHz, at a distance of 100 jim. To better understand its performance, we developed a lumped-element, equivalent circuit model. Simulations show that the circuit model accurately represents the noise isolation characteristics of the Faraday cage. Finally, Faraday cage design guidelines for optimum noise isolation are outlined.by Joyce H. Wu.Ph.D

Mechanics, mechanisms, and modeling of the chemical mechanical polishing process

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2001.Includes bibliographical references.The ever-increasing demand for high-performance microelectronic devices has motivated the semiconductor industry to design and manufacture Ultra-Large-Scale Integrated (ULSI) circuits with smaller feature size, higher resolution, denser packing, and multi-layer interconnects. The ULSI technology places stringent demands on global planarity of the Interlevel Dielectric (ILD) layers. Compared with other planarization techniques, the Chemical Mechanical Polishing (CMP) process produces excellent local and global planarization at low cost. It is thus widely adopted for planarizing inter-level dielectric (silicon dioxide) layers. Moreover, CMP is a critical process for fabricating the Cu damascene patterns, low-k dielectrics, and shallow isolated trenches. The wide range of materials to be polished concurrently or sequentially, however, increases the complexity of CMP and necessitates an understanding of the process fundamentals for optimal process design. This thesis establishes a theoretical framework to relate the process parameters to the different wafer/pad contact modes to study the behavior of wafer-scale polishing. Several models of polishing - microcutting, brittle fracture, surface melting and burnishing - are reviewed. Blanket wafers coated with a wide range of materials are polished to verify the models. Plastic deformation is identified as the dominant mechanism of material removal in fine abrasive polishing.(cont.) Additionally, contact mechanics models, which relate the pressure distribution to the pattern geometry and pad elastic properties, explain the die-scale variation of material removal rate (MRR) on pattern geometry. The pad displacement into low features of submicron lines is less than 0.1 nm. Hence the applied load is only carried by the high features, and the pressure on high features increases with the area fraction of interconnects. Experiments study the effects of pattern geometry on the rates of pattern planarization, oxide overpolishing and Cu dishing. It was observed that Cu dishing of submicron features is less than 20 nm and contributes less to surface non-uniformity than does oxide overpolishing. Finally, a novel in situ detection technique, based on the change of the reflectance of the patterned surface at different polishing stages, is developed to detect the process endpoint and minimize overpolishing. Models that employ light scattering theory and statistical treatment correlate the sampled reflectance with the surface topography and Cu area fraction for detecting the process regime and endpoint. The experimental results agree well with the endpoint detection schemes predicted by the models.by Jiun-Yu Lai.Ph.D

A novel low-swing voltage driver design and the analysis of its robustness to the effects of process variation and external disturbances

arket forces are continually demanding devices with increased functionality/unit area; these demands have been satisfied through aggressive technology scaling which, unfortunately, has impacted adversely on the global interconnect delay subsequently reducing system performance. Line drivers have been used to mitigate the problems with delay; however, these have a large power consumption. A solution to reducing the power dissipation of the drivers is to use lower supply voltages. However, by adopting a lower power supply voltage, the performance of the line drivers for global interconnects is impaired unless low-swing signalling techniques are implemented. Low-swing signalling techniques can provide high speed signalling with low power consumption and hence can be used to drive global on-chip interconnect. Most of the proposed low-swing signalling schemes are immune to noise as they have a good SNR. However, they tend to have a large penalty in area and complexity as they require additional circuitry such as voltage generators and low-Vth devices. Most of the schemes also incorporate multiple Vdd and reference voltages which increase the overall circuit complexity. A diode-connected driver circuit has the best attributes over other low-swing signalling techniques in terms of low power, low delay, good SNR and low area overhead. By incorporating a diode-connected configuration at the output, it can provide high speed signalling due to its high driving capability. However, this configuration also has its limitations as it has issues with its adaptability to process variations, as well as an issue with leakage currents. To address these limitations, two novel driver schemes have been designed, namely, nLVSD and mLVSD, which, additionally, have improvements in performance and power consumption. Comparisons between the proposed schemes with the existing diode-connected driver circuits (MJ and DDC) showed that the nLVSD and mLVSD drivers have approximately 46% and 50% less delay. The name MJ originates from the driver’s designer called Juan A. Montiel-Nelson, while DDC stands for dynamic diode-connected. In terms of power consumption, the nLVSD and mLVSD drivers also produce 43% and 7% improvement. Additionally, the mLVSD driver scheme is the most robust as its SNR is 14 to 44% higher compared to other diode-connected driver circuits. On the other hand, the nLVSD driver has 6% lower SNR compared to the MJ driver, even though it is 19% more robust than the DDC driver. However, since its SNR is still above 1, its improved performance and reduced power consumption, as well other advantages it has over other diode-connected driver circuits can compensate for this limitation. Regarding the robustness to external disturbances, the proposedmdriver circuits are more robust to crosstalk effects as the nLVSD and mLVSD drivers are approximately 35% and 7% more robust than other diode-connected drivers. Furthermore, the mLVSD driver is 5%, 33% and 47% more tolerant to SEUs compared to the nLVSD, MJ and DDC driver circuits respectively, whilst the MJ and DDC drivers are 26% and 40% less tolerant to SEUs iii compared to the nLVSD circuit. A comparison between the four schemes was also undertaken in the presence of ±3σ process and voltage (PV) variations. The analysis indicated that both proposed driver schemes are more robust than other diode-connected driver schemes, namely, the MJ and DDC driver circuits. The MJ driver scheme deviates approximately 18% and 35% more in delay and power consumption compared to the proposed schemes. The DDC driver has approximately 20% and 57% more variations in delay and power consumption in comparison to the proposed schemes. In order to further improve the robustness of the proposed driver circuits against process variation and environmental disturbances, they were further analysed to identify which process variables had the most impact on circuit delay and power consumption, as well as identifying several design techniques to mitigate problems with environmental disturbances. The most significant process parameters to have impact on circuit delay and power consumption were identified to be Vdd, tox, Vth, s, w and t. The impact of SEUs on the circuit can be reduced by increasing the bias currents whilst design methods such as increasing the interconnect spacing can help improve the circuit robustness against crosstalk. Overall it is considered that the proposed nLVSD and mLVSD circuits advance the state of the art in driver design for on-chip signalling applications.EThOS - Electronic Theses Online ServiceGBUnited Kingdo