Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Fully-integrated mm-Wave Full-duplexing and MIMO Multi-beamforming Receiver Techniques for 5G and Beyond

In recent years, the research community's interest in fully integrated mm-Wave wireless communication systems has increased significantly. With the standards for 5G NR now in place, the focus has shifted to actual deployment. Mm-Wave systems provide wider bandwidths, higher capacity, and lower latency than existing systems such as 4G. Higher path loss and shadowing, however, limit the network coverage at mm-Wave frequencies. The possibility of beamforming due to compact antenna size at mm-Wave and range-extending repeaters help mitigate challenges arising from path loss and relax link budget requirements. In the first part of the thesis, fully integrated scalable MIMO multi-beamforming phased-array to enable unit-tile based densely packed (lambda=2) large scale phased-arrays is demonstrated. Large scale arrays enhance Signal to Noise Ratio (SNR) and/or Effective Isotropically Radiated Power (EIRP) and help meet link budget. In the second part, mm-Wave Full-duplex (FD) receiver (RX) to implement Integrated Access and Backhaul (IAB) and repeaters in a spectrum efficient way is demonstrated. Dense deployment of IAB and repeaters enhances link robustness and range of connectivity. Two Integrated Chips (ICs) are fabricated and measured for demonstration. In the first IC, a 4-element MIMO RX array with multi-beamforming and simplified single wire intermediate frequency (IF) IO is presented. The evolution of mm-wave phased array receivers to MIMO RX promises multi-beamforming and improved capacity. Digital Beamforming (DBF) provides the highest flexibility for multibeamforming. However, it suffers from # of ADCs scaling with the # of elements and absence of spatial filtering prior to the ADCs. Mm-Wave MIMO arrays must also address the challenge of increased IO routing while supporting dense ll-factors with =2 antenna spacing. In this work, a MIMO multi-beamforming RX array architecture with simultaneous spatial filtering and single wire Frequency-domain Multiplexing (FDM) for 5G and beyond is presented. The proposed system preserves full MIMO field-of-view while ensuring a single IF interface. A 28 GHz 4-element RX prototype demonstrates the proposed functionality in 65-nm CMOS. The IC occupies only 3.4mm x 3.1mm for a four-element MIMO 28 GHz array and can form four independent beams with > 400MHz 3 dB BW and FDM on to a single IF interface. Mm-wave MIMO operation is demonstrated by concurrent reception of two wireless 28 GHz beams at 400 Mb/s (100 Msps, 16QAM) data rate. In the second IC, a 26-GHz fully integrated In-band Full-duplex (IBFD) Circulator receiver, which employs passive and active Self-interference Cancellation (SIC) techniques in the mm-Wave domain is presented. Coverage of wireless networks at mm-Wave frequencies can be enhanced by deploying a large number of base stations economically using wireless backhauling. Integrated access and backhaul nodes with spectrum reuse is an efficient way of wireless backhauling. To retain the channel capacity, IAB needs to be implemented using FD schemes that suffers from a strong Transmitter (TX) to RX leakage. This SI leakage can significantly impact the receiver sensitivity and increase the baseband/ADC dynamic range requirements. Canceling SI at mm-Wave applications is challenging given the high frequency of operation, wide bandwidths, and antenna (ANT) impedance sensitivity to the surroundings. Proposed mm-Wave RX with a shared ANT interface based on a Circulator with active SI cancelers provide ~53 dB SIC over 400MHz and ~40 dB SIC over 400MHz to meet the link budget requirements. Proposed architecture achieves SIC by (i) introducing a shared ANT interface based on a hybrid-coupler and a Non-reciprocal Transmission Line (NTL) that provides wideband SIC and additionally creating a SI replica (ii) subsequent active cancellation using SI replica along with variable gain and phase shifters to accommodate SI channel variations. Proposed 26-GHz RX consumes only ~111mW power. The system is implemented in 45nm SOI CMOS and has an active area of 4.54mm². Stand-alone RX NF is ~5.8 dB, and TX to ANT Insertion Loss (IL) is ~3.1 dB. Over-the-Air (OTA) measurements with modulated TX (128 QAM 2.1 Gb/s) and RX (128 QAM 4.2 Gb/s) signals show an EVM of 3.3% when PTX = PRX

RF and Millimeter-wave Techniques to Improve Scalability and Efficiency of Digital Beamforming Arrays

Spectrum overcrowding, ever increasing demand for high data rate and increased mobility requirements are three major challenges 5G-technology is trying to address. In this thesis I start with a RF front-end technique that deals with blocker interference arising from spectrum overcrowding both across frequency bands and within the same frequency bands. Chapter 3 presents a single wire IF interface design for phased array receivers which enables simple IF backhaul for high data volume MIMO systems. Finally a outphasing power amplifier(PA) design is presented in chapter 4 along with a driver amplifier with digital amplitude modulation to achieve state of the art power back off efficiency, which reduces battery usage and thus increases mobility. The first part of this thesis demonstrates the use of orthogonal sequences along to N-path filters to achieve reconfigurable select/reject filtering of signals based on their spatial, spectral and code-domain properties. A frequency/code-domain reject and select filtering is proposed and implemented using N-path switching with passive inductors as correlators. Using inductors instead of capacitors in N-path filters is challenging because of large inductance value required for our application demands use of off-chip inductors, which comes with associated parasitics and lower self-resonance frequency. In this design a cascaded inductor approach and differential N-path filtering is used to overcome inductor parasitics and enable operation at 1 GHz. A code-domain notch filter followed by a code-domain select receiver is designed and implemented in 65-nm CMOS technology. Measurements demonstrate 0.5 GHz to 1.0 GHz filter tuning range, with a maximum 26dB rejection for a blocker signal with 8dBm power, while consuming 60mW (at 1GHz operation frequency) and occupying 1.2mm2 of die area. Second part of this thesis demonstrates a single wire IF interface to simplify scaling of millimeter-wave(mm-Wave) phased array systems while preserving the data from each element, this enables spatial multiplexing, virtual arrays for radar, digital beamforming(DBF), etc. However, per-element digitization results in a formidable I/O challenge in large-scale tiled MIMO mm-Wave arrays. This dissertation demonstrates a 28 GHz 4-element MIMO RX with a single-wire interface that multiplexes the baseband signals of all elements and the LO reference through code-domain multiplexing. System considerations are presented and the approach is validated through DBF after de-multiplexing of the baseband signals from the single wire. Each element in the array achieves 16 dB conversion gain and ∼ 7 dB noise figure(NF) while consuming 60 mA from 1.2 V. The IC occupies 5.75 mm² in 65-nm CMOS. Final part of this thesis describes the design and implementation of a digital outphasing PA at 28 GHz to achieve state of the art back of efficiency. Outphasing PA require branch PA units to act as voltage sources(very low output impedance), which is challenging at mm-Wave frequencies. In this PA design an approximate class-F operation is achieved by tuning PA load network for up to 3rd harmonic. A stacked PA architecture is used for individual PA units to achieve high maximum power output. Output-power further improved by utilizing a novel diode connected stack bias circuit to improve out-put swing. PA delivers a maximum output-power of 20 dBm with a peak power added efficiency(PAE) of 27% (PA along with driver stages) and 6 dB back-off PAE of 16.5%

I/Q Imbalance in Multiantenna Systems: Modeling, Analysis and RF-Aware Digital Beamforming

Wireless communications has experienced an unprecedented increase in data rates, numbers of active devices and selection of applications during recent years. However, this is expected to be just a start for future developments where a wireless connection is seen as a fundamental resource for almost any electrical device, no matter where and when it is operating. Since current radio technologies cannot provide such services with reasonable costs or even at all, a multitude of technological developments will be needed. One of the most important subjects, in addition to higher bandwidths and flexible network functionalities, is the exploitation of multiple antennas in base stations (BSs) as well as in user equipment (UEs). That kind of multiantenna communications can boost the capacity of an individual UE-BS link through spatial antenna multiplexing and increase the quality as well as robustness of the link via antenna diversity. Multiantenna technologies provide improvements also on the network level through spatial UE multiplexing and sophisticated interference management. Additionally, multiple antennas can provide savings in terms of the dissipated power since transmission and reception can be steered more efficiently in space, and thus power leakage to other directions is decreased. However, several issues need to be considered in order to get multiantenna technologies widely spread. First, antennas and the associated transceiver chains are required to be simple and implementable with low costs. Second, size of the antennas and transceivers need to be minimized. Finally, power consumption of the system must be kept under control. The importance of these requirements is even emphasized when considering massive multiple-input multiple-output (MIMO) systems consisting of devices equipped with tens or even hundreds of antennas.In this thesis, we consider multiantenna devices where the associated transceiver chains are implemented in such a way that the requirements above can be met. In particular, we focus on the direct-conversion transceiver principle which is seen as a promising radio architecture for multiantenna systems due to its low costs, small size, low power consumption and good flexibility. Whereas these aspects are very promising, direct-conversion transceivers have also some disadvantages and are vulnerable to certain imperfections in the analog radio frequency (RF) electronics in particular. Since the effects of these imperfections usually get even worse when optimizing costs of the devices, the scope of the thesis is on the effects and mitigation of one of the most severe RF imperfection, namely in-phase/quadrature (I/Q) imbalance.Contributions of the thesis can be split into two main themes. First of them is multiantenna narrowband beamforming under transmitter (TX) and receiver (RX) I/Q imbalances. We start by creating a model for the signals at the TX and RX, both under I/Q imbalances. Based on these models we derive analytical expressions for the antenna array radiation patterns and notice that I/Q imbalance distorts not only the signals but also the radiation characteristics of the array. After that, stemming from the nature of the distortion, we utilize widely-linear (WL) processing, where the signals and their complex conjugates are processed jointly, for the beamforming task under I/Q imbalance. Such WL processing with different kind of statistical and adaptive beamforming algorithms is finally shown to provide a flexible operation as well as distortion-free signals and radiation patterns when being under various I/Q imbalance schemes.The second theme extends the work to wideband systems utilizing orthogonal frequency-division multiplexing (OFDM)-based waveforms. The focus is on uplink communications and BS RX processing in a multiuser MIMO (MU-MIMO) scheme where spatial UE multiplexing is applied and further UE multiplexing takes place in frequency domain through the orthogonal frequency-division multiple access (OFDMA) principle. Moreover, we include the effects of external co-channel interference into our analysis in order to model the challenges in heterogeneous networks. We formulate a flexible signal model for a generic uplink scheme where I/Q imbalance occurs on both TX and RX sides. Based on the model, we analyze the signal distortion in frequency domain and develop augmented RX processing methods which process signals at mirror subcarrier pairs jointly. Additionally, the proposed augmented methods are numerically shown to outperform corresponding per-subcarrier method in terms of the instantaneous signal-to-interference-and-noise ratio (SINR). Finally, we address some practical aspects and conclude that the augmented processing principle is a promising tool for RX processing in multiantenna wideband systems under I/Q imbalance.The thesis provides important insight for development of future radio networks. In particular, the results can be used as such for implementing digital signal processing (DSP)-based RF impairment mitigation in real world transceivers. Moreover, the results can be used as a starting point for future research concerning, e.g., joint effects of multiple RF impairments and their mitigation in multiantenna systems. Overall, this thesis and the associated publications can help the communications society to reach the ambitious aim of flexible, low-cost and high performance radio networks in the future

Integrated Self-Interference Cancellation for Full-Duplex and Frequency-Division Duplexing Wireless Communication Systems

From wirelessly connected robots to car-to-car communications, and to smart cities, almost every aspect of our lives will benefit from future wireless communications. While promise an exciting future world, next-generation wireless communications impose requirements on the data rate, spectral efficiency, and latency (among others) that are higher than those for today's systems by several orders of magnitude. Full-duplex wireless, an emergent wireless communications paradigm, breaks the long-held assumption that it is impossible for a wireless device to transmit and receive simultaneously at the same frequency, and has the potential to immediately double network capacity at the physical (PHY) layer and offers many other benefits (such as reduced latency) at the higher layers. Recently, discrete-component-based demonstrations have established the feasibility of full-duplex wireless. However, the realization of integrated full duplex radios, compact radios that can fit into smartphones, is fraught with fundamental challenges. In addition, to unleash the full potential of full-duplex communication, a careful redesign of the PHY layer and the medium access control (MAC) layer using a cross-layer approach is required. The biggest challenge associated with full duplex wireless is the tremendous amount of transmitter self-interference right on top of the desired signal. In this dissertation, new self-interference-cancellation approaches at both system and circuit levels are presented, contributing towards the realization of full-duplex radios using integrated circuit technology. Specifically, these new approaches involve elimination of the noise and distortion of the cancellation circuitry, enhancing the integrated cancellation bandwidth, and performing joint radio frequency, analog, and digital cancellation to achieve cancellation with nearly one part-per-billion accuracy. In collaboration with researchers at higher layers of the stack, a cross-layer approach has been used in our full-duplex research and has allowed us to derive power allocation algorithms and to characterize rate-gain improvements for full-duplex wireless networks. To enable experimental characterization of full-duplex MAC layer algorithms, a cross-layered software-defined full-duplex radio testbed has been developed. In collaboration with researchers from the field of micro-electro-mechanical systems, we demonstrate a multi-band frequency-division duplexing system using a cavity-filter-based tunable duplexer and our integrated widely-tunable self-interference-cancelling receiver

Energy-Efficient Wireless Connectivity and Wireless Charging For Internet-of-Things (IoT) Applications

During the recent years, the Internet-of-Things (IoT) has been rapidly evolving. It is indeed the future of communication that has transformed Things of the real world into smarter devices. To date, the world has deployed billions of “smart” connected things. Predictions say there will be 10’s of billions of connected devices by 2025 and in our lifetime we will experience life with a trillion-node network. However, battery lifespan exhibits a critical barrier to scaling IoT devices. Replacing batteries on a trillion-sensor scale is a logistically prohibitive feat. Self-powered IoT devices seems to be the right direction to stand up to that challenge. The main objective of this thesis is to develop solutions to achieve energy-efficient wireless-connectivity and wireless-charging for IoT applications. In the first part of the thesis, I introduce ultra-low power radios that are compatible with the Bluetooth Low-Energy (BLE) standard. BLE is considered as the preeminent protocol for short-range communications that support transmission ranges up to 10’s of meters. Number of low power BLE transmitter (TX) and receiver (RX) architectures have been designed, fabricated and tested in different planar CMOS and FinFET technologies. The low power operation is achieved by combining low power techniques in both the network and physical layers, namely: backchannel communication, duty-cycling, open-loop transmission/reception, PLL-less architectures, and mixer-first architectures. Further novel techniques have been proposed to further reduce the power the consumption of the radio design, including: a fast startup time and low startup energy crystal oscillators, an antenna-chip co-design approach for quadrature generation in the RF path, an ultra-low power discrete-time differentiator-based Gaussian Frequency Shift Keying (GFSK) demodulation scheme, an oversampling GFSK modulation/demodulation scheme for open loop transmission/reception and packet synchronization, and a cell-based design approach that allows automation in the design of BLE digital architectures. The implemented BLE TXs transmit fully-compliant BLE advertising packet that can be received by commercial smartphone. In the second part of the thesis, I introduce passive nonlinear resonant circuits to achieve wide-band RF energy harvesting and robust wireless power transfer circuits. Nonlinear resonant circuits modeled by the Duffing nonlinear differential equation exhibit interesting hysteresis characteristics in their frequency and amplitude responses that are exploited in designing self-adaptive wireless charging systems. In the magnetic-resonance wireless power transfer scenario, coupled nonlinear resonators are proposed to maintain the power transfer level and efficiency over a range of coupling factors without active feedback control circuitry. Coupling factor depends on the transmission distance, lateral, and angular misalignments between the charging pad and the device. Therefore, nonlinear resonance extends the efficient charging zones of a wireless charger without the requirement for a precise alignment.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/169842/1/omaratty_1.pd

CMOS Front-End Circuits in 45-nm SOI Suitable for Modular Phased-Array 60-GHz Radios

Next Fifth-generation (5G) wireless technologies enabling ultra-wideband spectrum availability and increased system capacity can achieve multi-gigabit/s (Gbps) data rates suitable for ultra-high-speed internet access around the 60-GHz band (i.e., Wi-Gig Technology). This mm-wave band is unlicensed and experiences high propagation power losses. Therefore, it is suitable for short-range communications and requires antenna arrays to satisfy the link budget requirements. Half-duplex reconfigurable phased-array transceivers require wideband, low-cost, highly integrated front-end circuits such as bilateral RF switches, low-noise/power amplifiers, passive RF splitters/combiners, and phase shifters implemented in deep sub-micron CMOS. In this dissertation, analysis, design, and verification of essential CMOS front-end components are covered and fabricated in GlobalFoundries 45-nm RF-SOI CMOS technology. Firstly, a fully-differential, single-pole, single-throw (SPST) switch capable of high isolation in broadband CMOS transceivers is described. The SPST switch realizes better than 50-dB isolation (ISO) across DC to 43 GHz while maintaining an insertion loss (IL) below 3 dB. Measured RF input power for 1-dB compression (IP1dB) of the IL is +19.6 dBm, and the measured input third-order intercept point (IIP3) is +30.4 dBm (both assuming differential inputs at 20 GHz). The prototype has an active area of 0.0058 mm^2. Secondly, a single-pole double-throw (SPDT) switch is implemented using the SPST concept by using a balun to convert the shared differential path to a single-ended antenna port. The SPDT simulations predict less than 3.5-dB IL and greater than 40-dB ISO across 55 to 65 GHz frequency band. An IP1dB of +21 dBm is expected from large-signal simulations. The prototype has an active area of 0.117 mm^2. Thirdly, a fully-differential switched-LC topology adopted with slow-wave artificial transmission line concept, and phase inversion network is described for a 360-degree phase shift range with 11.25-degree phase resolution. The average IL of the complete phase shifter is 5.3 dB with less than 1-dB rms IL error. Furthermore, the IP1dB of the phase shifter is +16 dBm. The prototype has an active area of 0.245 mm^2. Lastly, a fully-differential, 2-stage, common-source (CS) low-noise amplifier (LNA) is developed with wideband matching from 57.8 GHz to 67 GHz, a maximum simulated forward power gain of 20.8 dB, and a minimum noise figure of 3.07 dB. The LNA consumes 21 mW and predicts an OP1dB of 4.8 dBm from the 1-V supply. The LNA consumes an active area of 0.028 mm^2