7 research outputs found
A physical design and layout versus schematic framework for superconducting electronics
Thesis (MEng)--Stellenbosch University, 2021.ENGLISH ABSTRACT: This dissertation presents a PCell synthesis and layout vs schematic extraction framework, named SPiRA. This framework allows the user to create a
PCell-based layout, creating parameters to adjust polygon positions, sizes and
presence. All polygons are connected to a specific layer in the fabrication
process by means of a suggested Rule Deck Database containing process information. During the creation of a PCell, an undirected graph or node graph,
showing all the interconnections present in the layout, is generated. Furthermore a SPICE-like netlist (a list containing information about the elements
contained in the circuit and how element ports are connected) is generated by
parsing this node network allowing the user to see if the extracted elements
match up with the initial design. SPiRA is a Python framework, allowing for
dynamicity in the creation of the layout, giving the user feedback along the
way. Design rule checking (DRC) is implemented by means of different parameter types, allowing the user to get feedback during the creation of the layout
about broken design rules. Further, full post-layout DRC is implemented by
means of the KLayout DRC engine. As a futher extension of the framework,
SPiRA-tools is introduced. This collection of tools allows the user to modify
a layout, to prepare it for simulation by means of the InductEx simulation
engine. SPiRA-tools also brings to life a schematic generator, that reads in a
netlist file to produce a Standard Vector Graphics schematic, allowing the user
to visually compare initial design, with the newly generated output allowing
for true Layout vs Schematic comparison.AFRIKAANSE OPSOMMING: Die dissertasie bied ’n geparametriseerde sell (PCell) sintese raamwerk met
LVS (Layout vs Schematic) funksionaliteit ingebou, genaamd SPiRA. Hierdie
raamwerk gee die gebruiker die funksionaliteit om ’n PCell te maak, wat
verstelbaarheid aan die posisie, grote en teenwoordigheid van enige veelhoek
in die stroombaan gee. Vervaardigingsprosesreëls en prosesdata word in ’n
Reëldatabase (RDD) gestoor, om hergebruik te word deur stroombaanontwerpers gedurende die uitleg van ’n geparameteriseerde sel. ’n Ongerigte node
grafiek/netwerk word gegenereer wanneer ’n gaparametriseerde sel geïnstansieer word. Hierdie grafiek dui al die interkonneksies van die gegewe stroombaan aan. Hierdie netwerk word dan verder reduseer om ’n geskikte netlist
(soortgelyk aan SPICE) te produseer wat werk met die simulasiesagteware,
InductEx. Hierdie netlist kan met die oorspronklike ontwerp vergelyk word om
te bepaal of al die konneksies en grote van die stroombaanelemente ooreenstem. Aangesien SPiRA op die skriptaal, Python, gebaseer is, kan dinamiese
terugvoer vir die gebruiker gegee word tydens seluitleg. Ontwerpreëlkontrole is
in plek gestel deur middel van gespesialiseerde SPiRA parameters, wat die gebruiker inkennis stel wanneer ’n ontwerpreël gebreek word. Verder het SPiRA
die funksionaliteit om volle selontwerpe te kan analiseer met behulp van KLayout se losstaande ontwerpreëlkontrole sagteware. SPiRA-tools is ’n ekstensie
van SPiRA wat streef om ’n Standard Vector Graphic lêer te produseer, wat
die visuele voorstelling van ’n gegewe netlist is. Hierdie visuele voorstelling van
die stroombaan kan dan direk met die oorspronklike ontwerp vergelyk word,
vir ware Layout vs Schematic vergelykbaarheid.Master
Space Communications: Theory and Applications. Volume 3: Information Processing and Advanced Techniques. A Bibliography, 1958 - 1963
Annotated bibliography on information processing and advanced communication techniques - theory and applications of space communication
Understanding Quantum Technologies 2022
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