Implementation of IEEE 32 Bit Single Precision Floating Point Addition and Subtraction

ABSTRACT This paper presents a floating-point addition and subtraction algorithm and their pipeline design. Floating point unit have different operations which is hard to implement on FPGAs due to complexity of their algorithms. Many scientific applications require more accuracy in result. For that reason, we have explored implementation of addition and subtraction for IEEE single precision floating point numbers. We implemented trade-off between area and speed for accuracy. We have implemented adder and subtractor as a bit-parallel adder. The algorithms are designed in VHDL language and can be implemented on FPGA kit by use of Xilinx ISE compiler. Floating point adder and subtractor unit design using pipeling which provides high performance and increase the speed.it used for execute multiple instructions simultaneously. The language is used for coding is VHDL and tool is Xlinix ISE

Low Power Synchronous Design of Hardware Architecture for Ieee 754 Single Precision Floating Point Fast Fourier Transform

Signal Processing, communication systems, Digital information systems and many other fields of DSP have the wide need for Fast Fourier Transformation computations. Hardware architecture for computing IEEE 754 single precision floating point FFT is proposed here and the work is focused on power optimization of the design. Cooley-Tukey�s (DIF) Decimation in Frequency domain butterfly algorithm is used for the design implementation. Proposed design is a synchronous architecture and proved to be an efficient compared to the earlier parallel architectures. The clock latency and hardware over head of the design is productive and cost effective compared to the designs known earlier. The design is implemented in RTL Verilog and logically verified using Altera-Model Sim. Synthesis of the design is carried out in gscl-45 nm library, 1.1 v process using Synopsys design vision and prime time tools. The power reports showed that the proposed design consumes 90% less power with 50% reduced clock latency compared to earlier designs. Frequency of the design is compromised to an extent but can be improved using the suggested novel sub-designs of floating point add/sub and multiply blocks. Techniques for further power optimization are also given for future implementations.Electrical Engineerin