Rapid mapping of digital integrated circuit logic gates via multi-spectral backside imaging

Modern semiconductor integrated circuits are increasingly fabricated at untrusted third party foundries. There now exist myriad security threats of malicious tampering at the hardware level and hence a clear and pressing need for new tools that enable rapid, robust and low-cost validation of circuit layouts. Optical backside imaging offers an attractive platform, but its limited resolution and throughput cannot cope with the nanoscale sizes of modern circuitry and the need to image over a large area. We propose and demonstrate a multi-spectral imaging approach to overcome these obstacles by identifying key circuit elements on the basis of their spectral response. This obviates the need to directly image the nanoscale components that define them, thereby relaxing resolution and spatial sampling requirements by 1 and 2 - 4 orders of magnitude respectively. Our results directly address critical security needs in the integrated circuit supply chain and highlight the potential of spectroscopic techniques to address fundamental resolution obstacles caused by the need to image ever shrinking feature sizes in semiconductor integrated circuits

Defeating microprobing attacks using a resource efficient detection circuit

Microprobing is an attack technique against integrated circuits implementing security functions, such as OTP tokens or smartcards. It allows intercepting secrets from onchip wires as well as injecting faults for other attacks. While the necessity to etch open chip packages and to remove the passivation layer makes microprobing appear expensive, it was shown that a successful attack can be run with equipment worth a few thousand euros. On the protector’s side, however, appropriate countermeasures such as active shields, redundancy of core components, or analog detection circuits containing large capacitors, are still expensive. We present a resource efficient microbing detection circuit that we call Low Area Probing Detector (LAPD). It measures minimal timing differences between on-chip wires caused by the capacitive load of microprobes. Simulations show that it can detect up-todate probes with capacitances as low as 10 fF. As a novelty, the LAPD is merely based on digital components and does not require analog circuitry, which reduces the required area and process steps compared to previous approaches.Postprint (author’s final draft

The low area probing detector as a countermeasure against invasive attacks

© 20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksMicroprobing allows intercepting data from on-chip wires as well as injecting faults into data or control lines. This makes it a commonly used attack technique against security-related semiconductors, such as smart card controllers. We present the low area probing detector (LAPD) as an efficient approach to detect microprobing. It compares delay differences between symmetric lines such as bus lines to detect timing asymmetries introduced by the capacitive load of a probe. Compared with state-of-the-art microprobing countermeasures from industry, such as shields or bus encryption, the area overhead is minimal and no delays are introduced; in contrast to probing detection schemes from academia, such as the probe attempt detector, no analog circuitry is needed. We show the Monte Carlo simulation results of mismatch variations as well as process, voltage, and temperature corners on a 65-nm technology and present a simple reliability optimization. Eventually, we show that the detection of state-of-the-art commercial microprobes is possible even under extreme conditions and the margin with respect to false positives is sufficient.Peer ReviewedPostprint (author's final draft

3D Integration: Another Dimension Toward Hardware Security

We review threats and selected schemes concerning hardware security at design and manufacturing time as well as at runtime. We find that 3D integration can serve well to enhance the resilience of different hardware security schemes, but it also requires thoughtful use of the options provided by the umbrella term of 3D integration. Toward enforcing security at runtime, we envision secure 2.5D system-level integration of untrusted chips and "all around" shielding for 3D ICs.Comment: IEEE IOLTS 201

Contactless visible light probing for nanoscale ICs through 10 μm bulk silicon

This paper explains why only optical techniques will be able to provide debug and diagnosis of bulk silicon FinFET technologies. In order to apply optical techniques through a convenient thickness of silicon on the one hand, light is limited to NIR to minimize absorption. To match resolution requirements on the other hand, it becomes mandatory to use shorter wavelengths. Two key issues have to be addressed: First, the penetration depth of visible light is only a few μm. This challenges device preparation and integrity. Our approach makes use of confocal microscopy suppressing back surface reflection and thus relaxing the preparation requirements to around 10 μm. Second, only solid immersion lenses (SIL) enable nanoscale resolution. But instead of silicon, materials transparent to visible light and providing a high refractive index are necessary. Our concept is based on 658 nm/633 nm laser and supports GaP as SIL material. We demonstrate the power of confocal imaging and prove contactless probing through a device thickness of 10 μm. We discuss how confocal optics relax the thickness requirements for visible light imaging and probing and we layout the concept for a GaP SIL. This concept opens the path to the design of nanoscale visible light debug and diagnosis

Perspectives of Nuclear Physics in Europe: NuPECC Long Range Plan 2010

The goal of this European Science Foundation Forward Look into the future of Nuclear Physics is to bring together the entire Nuclear Physics community in Europe to formulate a coherent plan of the best way to develop the field in the coming decade and beyond.<p></p> The primary aim of Nuclear Physics is to understand the origin, evolution, structure and phases of strongly interacting matter, which constitutes nearly 100% of the visible matter in the universe. This is an immensely important and challenging task that requires the concerted effort of scientists working in both theory and experiment, funding agencies, politicians and the public.<p></p> Nuclear Physics projects are often “big science”, which implies large investments and long lead times. They need careful forward planning and strong support from policy makers. This Forward Look provides an excellent tool to achieve this. It represents the outcome of detailed scrutiny by Europe’s leading experts and will help focus the views of the scientific community on the most promising directions in the field and create the basis for funding agencies to provide adequate support.<p></p> The current NuPECC Long Range Plan 2010 “Perspectives of Nuclear Physics in Europe” resulted from consultation with close to 6 000 scientists and engineers over a period of approximately one year. Its detailed recommendations are presented on the following pages. For the interested public, a short summary brochure has been produced to accompany the Forward Look.<p></p&gt