Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s

High-Gain Transimpedance Amplifier With DC Photodiode Current Rejection

This master\u27s thesis deals with the design of a differential high-gain transimpedance amplifier in TSMC\u27s 0.18 um mixed signal process that utilizes a DC photodiode current cancellation loop and a switching automatic gain control (AGC) with a bilinear gain curve. The amplifier is designed to satisfy the demands of Optical Coherence Tomography applications where the receiver is expected to measure the envelope power of an amplitude modulated sinusoidal optical signal that incorporates a large DC component. Methods of increasing dynamic range and gain linearity through the use of DC photodiode current cancellation and bilinear gain are explored. Effects of changing DC photodiode current on the overall system response is also demonstrated

PLANAR CMOS AND MULTIGATE TRANSISTORS BASED WIDE-BAND OTA BUFFER AMPLIFIERS FOR HEAVY RESISTANCE LOAD

Analog buffer amplifier configurations capable of driving heavy resistive load using different operational transconductance amplifier (OTA) are presented in this paper. The OTA CMOS buffer configurations are designed using 0.18 µm SCL technology library in Cadence Virtuoso tool and multigate transistor OTA buffer in TCAD Sentaurus tool. CMOS OTA buffer configuration using simple OTA outperform the OTA buffer circuits using other OTAs in terms of power dissipation and stability. Measured results show that the OTA buffer circuit works well for resistive load below 100 Ω. The gain tuning of up to 5 V/V is achieved with RL equal to 50 Ω, output swing of 1 V. OTA buffer configuration implemented using multigate transistor with resistive load below 1 kΩ exhibits a bandwidth around 5 GHz and tunable gain up to 5 V/V

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

A 2.5 GHz Optoelectronic Amplifier in 0.18 m CMOS

The ever-growing need for high speed data transmission is driven by multimedia and telecommunication demands. Traditional metallic media, such as copper coaxial cable, prove to be a limiting factor for high speed communications. Fiber optic methods provide a feasible solution that lacks the limitations of metallic mediums, including low bandwidth, cross talk caused by magnetic induction, and susceptibility to static and RF interferences. The first scientists to work with fibers optics started in 1970. One of the early challenges they faced was to produce glass fiber that was pure enough to be equal in performance with copper based media. Since then, the technology has advanced tremendously in terms of performance, quality, and consistency. The advancement of fiber optic communication has met its limits, not in the purity of its fiber media used to guide the data-modulated light wave, but in the conversion back and forth between electric signals to light. A high speed optic receiver must be used to convert the incident light into electrical signals. This thesis describes the design of a 2.5 GHz Optoelectronic Amplifier, the front end of an optic receiver. The discussion includes a survey of feasible topologies and an assessment of circuit techniques to enhance performance. The amplifier was designed and realized in a TSMC 0.18 µm CMOS process

Monolithic large-signal transimpedance amplifier for use in multi-gigabit, short-range optoelectronic interconnect applications

Published versio

Auto-zero stabilized CMOS amplifiers for very low voltage or current offset

In this paper, we present two amplifiers designed in CMOS technology and including an auto-zero architecture for very low offset control