The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

PATH DELAY DESIGN-FOR-TESTABILITY USING SNOOPING FOR FUNCTIONAL REGISTER-TRANSFER LEVEL CIRCUITS

Testing of VLSI circuits is important to ensure the reliability of digital systems. Due to the advancement in process technology, more performance defects occur. Path delay testing ensures the timing accuracy and functional correctness of the VLSI circuits and has become crucial. The standard scan-based design-for-testability (DFT) does not support the path delay testing, and transforms faults in circuits, which do not affect its functionality (untestable faults), into testable faults. This causes over-testing which reduces the manufacturing yield. Among the scan approaches, only the enhanced scan (ES) gives a solution to test the path delay fault (PDF) with a large area overhead and a long test application time, and it does not support at-speed and functional RTL circuit testing. Recently, nonscan and hybrid methods have been used to perform PDF testing only for structural register-transfer level (RTL) circuits called separable controller-data path circuits. These approaches overcome the limitations of the ES, but still require large area overhead and a long test application time. This thesis proposes a hybrid delay DFT method for more general functional RTL circuits that are called nonseparable controller-data path circuits. A snooping mechanism as a diagnostic tool for RTL circuits is introduced to facilitate the testing of delay faults on control, status and functionally generated control signal lines in terms of observability. the data path module is transformed into a single-port change (SPC) two-pattern testable (TPT) data path which provides controllability and observability against each path and reduces the test generation (TG) time. The controller module is transformed into a parallel-scan (PS) controller that reduces the test application time (TAT). The method gives the same test quality as the ES approach, but reduces the area overhead and TAT, and it supports atspeed testing