Architecture, Design, and Implementation of a Rapidly Prototyped Virtual Environment for a Military Spaceplane

The new Global Engagement vision places increased emphasis on the Air Force\u27s ability to control and exploit space. A military spaceplane combining reliable access to space, high operational tempos, and multi-mission capabilities is in conceptual stages of development. Virtual environment technology provides an opportunity to investigate system requirements and unconventional interface paradigms for this unique vehicle. A virtual environment architecture and design based on support for a rapid prototyping development process, separation of concerns, and user interface development is presented. The rapid prototyping process allowed management of changing requirements via an evolutionary approach to implementation. Separation of the activities performed by the virtual environment into classes enabled high performance through computational distribution, prevented modifications from rippling through the system and impeding development, and promoted reuse of computation and geometric models. A technique was developed to reduce the flimmer induced by the large spatial extent of the virtual environment. The architecture succeeded in providing a flexible framework for the AFIT Virtual Spaceplane. The Virtual Spaceplane is a large-scale virtual environment within which an immersed user commands a military spaceplane through atmospheric and orbital regimes to complete several simulated missions via an unconventional virtual interface

Implementation of MP{_}Lite for the VI Architecture

MP{_}Lite is a light weight message-passing library designed to deliver the maximum performance to applications in a portable and user friendly manner. The Virtual Interface (VI) architecture is a user-level communication protocol that bypasses the operating system to provide much better performance than traditional network architectures. By combining the high efficiency of MP{_}Lite and high performance of the VI architecture, they are able to implement a high performance message-passing library that has much lower latency and better throughput. The design and implementation of MP{_}Lite for M-VIA, which is a modular implementation of the VI architecture on Linux, is discussed in this thesis. By using the eager protocol for sending short messages, MP{_}Lite M-VIA has much lower latency on both Fast Ethernet and Gigabit Ethernet. The handshake protocol and RDMA mechanism provides double the throughput that MPICH can deliver for long messages. MP{_}Lite M-VIA also has the ability to channel-bonding multiple network interface cards to increase the potential bandwidth between nodes. Using multiple Fast Ethernet cards can double or even triple the maximum throughput without increasing the cost of a PC cluster greatly

Design, Implementation, and Evaluation of Virtual Interface Architecture for Power PC Machines

The Virtual Interface Architecture (VIA) standard is a low-latency protocol that was designed for use in high-performance networks. VIA improves performance by reducing overhead in messaging. This research has two components. The first part of this research project is the development of a new tool for measuring the performance of a VIA implementation and comparing it to the more traditional high-overhead protocols used on the Internet. The development of the tool represents a significant contribution in and of itself, since the tool has been put into the public domain and will likely become useful by Lima users, both for measuring VIA networks, and as one of the first example codes available for learning how to write programs that use VIA. The new tool has exposed some interesting performance issues of VIA as the number of messages increases that are currently being examined. The second component of this research is the definition and development of appropriate interfaces from the network to the lowest level services in Lima on the Power PC platform, and the testing and evaluation of these functions. The research approach was to port a freely available implementation of VIA that runs on a Pentium platform to the Power PC platform. The architectural differences of the two platforms have raised a number of design and configuration issues that have been investigated and solved

Computing infrastructure issues in distributed communications systems : a survey of operating system transport system architectures

The performance of distributed applications (such as file transfer, remote login, tele-conferencing, full-motion video, and scientific visualization) is influenced by several factors that interact in complex ways. In particular, application performance is significantly affected both by communication infrastructure factors and computing infrastructure factors. Several communication infrastructure factors include channel speed, bit-error rate, and congestion at intermediate switching nodes. Computing infrastructure factors include (among other things) both protocol processing activities (such as connection management, flow control, error detection, and retransmission) and general operating system factors (such as memory latency, CPU speed, interrupt and context switching overhead, process architecture, and message buffering). Due to a several orders of magnitude increase in network channel speed and an increase in application diversity, performance bottlenecks are shifting from the network factors to the transport system factors.This paper defines an abstraction called an "Operating System Transport System Architecture" (OSTSA) that is used to classify the major components and services in the computing infrastructure. End-to-end network protocols such as TCP, TP4, VMTP, XTP, and Delta-t typically run on general-purpose computers, where they utilize various operating system resources such as processors, virtual memory, and network controllers. The OSTSA provides services that integrate these resources to support distributed applications running on local and wide area networks.A taxonomy is presented to evaluate OSTSAs in terms of their support for protocol processing activities. We use this taxonomy to compare and contrast five general-purpose commercial and experimental operating systems including System V UNIX, BSD UNIX, the x-kernel, Choices, and Xinu

The Octopus switch

This chapter1 discusses the interconnection architecture of the Mobile Digital Companion. The approach to build a low-power handheld multimedia computer presented here is to have autonomous, reconfigurable modules such as network, video and audio devices, interconnected by a switch rather than by a bus, and to offload as much as work as possible from the CPU to programmable modules placed in the data streams. Thus, communication between components is not broadcast over a bus but delivered exactly where it is needed, work is carried out where the data passes through, bypassing the memory. The amount of buffering is minimised, and if it is required at all, it is placed right on the data path, where it is needed. A reconfigurable internal communication network switch called Octopus exploits locality of reference and eliminates wasteful data copies. The switch is implemented as a simplified ATM switch and provides Quality of Service guarantees and enough bandwidth for multimedia applications. We have built a testbed of the architecture, of which we will present performance and energy consumption characteristics

An Object-Oriented Framework for Explicit-State Model Checking

This paper presents a conceptual architecture for an object-oriented framework to support the development of formal verification tools (i.e. model checkers). The objective of the architecture is to support the reuse of algorithms and to encourage a modular design of tools. The conceptual framework is accompanied by a C++ implementation which provides reusable algorithms for the simulation and verification of explicit-state models as well as a model representation for simple models based on guard-based process descriptions. The framework has been successfully used to develop a model checker for a subset of PROMELA

Design and Implementation of MPICH2 over InfiniBand with RDMA Support

For several years, MPI has been the de facto standard for writing parallel applications. One of the most popular MPI implementations is MPICH. Its successor, MPICH2, features a completely new design that provides more performance and flexibility. To ensure portability, it has a hierarchical structure based on which porting can be done at different levels. In this paper, we present our experiences designing and implementing MPICH2 over InfiniBand. Because of its high performance and open standard, InfiniBand is gaining popularity in the area of high-performance computing. Our study focuses on optimizing the performance of MPI-1 functions in MPICH2. One of our objectives is to exploit Remote Direct Memory Access (RDMA) in Infiniband to achieve high performance. We have based our design on the RDMA Channel interface provided by MPICH2, which encapsulates architecture-dependent communication functionalities into a very small set of functions. Starting with a basic design, we apply different optimizations and also propose a zero-copy-based design. We characterize the impact of our optimizations and designs using microbenchmarks. We have also performed an application-level evaluation using the NAS Parallel Benchmarks. Our optimized MPICH2 implementation achieves 7.6 $\mu$s latency and 857 MB/s bandwidth, which are close to the raw performance of the underlying InfiniBand layer. Our study shows that the RDMA Channel interface in MPICH2 provides a simple, yet powerful, abstraction that enables implementations with high performance by exploiting RDMA operations in InfiniBand. To the best of our knowledge, this is the first high-performance design and implementation of MPICH2 on InfiniBand using RDMA support.Comment: 12 pages, 17 figure