Implementation of a Hardware Algorithm for Integer Division

A hardware algorithm for integer division proposed by Naofumi Takagi, ShunsukeKadowaki and Kazuyoshi Takagi is implemented using the hardware-descriptive language called Verilog. The hardware algorithm is based on digit-recurrence non-restoring division. Each partial remainder is represented as an SD2 integer as a pair of its sign and absolute value. Quotient digit is obtained from the sign of every partial remainder with the most significant digit first. Quotient is obtained as an ordinary binary number and remainder as an SD2 integer. Remainder is converted from SD2 to binary using the concept of a carry lookahead adder. Combinational design for 4-bit and 8-bit integers that uses radix-2 signed-digit representation of numbers is implemented. It is simulated and tested using Mentor Graphics Corporation (MGC)® ModelSim™. RTL synthesis is performed and parameters like area, total cells, timing and power are calculated

Efficient Side-Channel Aware Elliptic Curve Cryptosystems over Prime Fields

Elliptic Curve Cryptosystems (ECCs) are utilized as an alternative to traditional public-key cryptosystems, and are more suitable for resource limited environments due to smaller parameter size. In this dissertation we carry out a thorough investigation of side-channel attack aware ECC implementations over finite fields of prime characteristic including the recently introduced Edwards formulation of elliptic curves, which have built-in resiliency against simple side-channel attacks. We implement Joye\u27s highly regular add-always scalar multiplication algorithm both with the Weierstrass and Edwards formulation of elliptic curves. We also propose a technique to apply non-adjacent form (NAF) scalar multiplication algorithm with side-channel security using the Edwards formulation. Our results show that the Edwards formulation allows increased area-time performance with projective coordinates. However, the Weierstrass formulation with affine coordinates results in the simplest architecture, and therefore has the best area-time performance as long as an efficient modular divider is available

Hardware implementation of elliptic curve Diffie-Hellman key agreement scheme in GF(p)

With the advent of technology there are many applications that require secure communication. Elliptic Curve Public-key Cryptosystems are increasingly becoming popular due to their small key size and efficient algorithm. Elliptic curves are widely used in various key exchange techniques including Diffie-Hellman Key Agreement scheme. Modular multiplication and modular division are one of the basic operations in elliptic curve cryptography. Much effort has been made in developing efficient modular multiplication designs, however few works has been proposed for the modular division. Nevertheless, these operations are needed in various cryptographic systems. This thesis examines various scalable implementations of elliptic curve scalar multiplication employing multiplicative inverse or field division in GF(p) focussing mainly on modular divison architectures. Next, this thesis presents a new architecture for modular division based on the variant of Extended Binary GCD algorithm. The main contribution at system level architecture to the modular division unit is use of counters in place of shift registers that are basis of the algorithm and modifying the algorithm to introduce a modular correction unit for the output logic. This results in 62% increase in speed with respect to a prototype design. Finally, using the modular division architecture an Elliptic Curve ALU in GF(p) was implemented which can be used as the core arithmetic unit of an elliptic curve processor. The resulting architecture was targeted to Xilinx Vertex2v6000-bf957 FPGA device and can be implemented for different elliptic curves for almost all practical values of field p. The frequency of the ALU is 58.8 MHz for 128-bits utilizing 20% of the device at 27712 gates which is 30% faster than a prototype implementation with a 2% increase in area utilization. The ALU was tested to perform Diffie-Hellman Key Agreement Scheme and is suitable for other public-key cryptographic algorithms

WEST-3 wind turbine simulator development

The software developed for WEST-3, a new, all digital, and fully programmable wind turbine simulator is given. The process of wind turbine simulation on WEST-3 is described in detail. The major steps are, the processing of the mathematical models, the preparation of the constant data, and the use of system software generated executable code for running on WEST-3. The mechanics of reformulation, normalization, and scaling of the mathematical models is discussed in detail, in particulr, the significance of reformulation which leads to accurate simulations. Descriptions for the preprocessor computer programs which are used to prepare the constant data needed in the simulation are given. These programs, in addition to scaling and normalizing all the constants, relieve the user from having to generate a large number of constants used in the simulation. Also given are brief descriptions of the components of the WEST-3 system software: Translator, Assembler, Linker, and Loader. Also included are: details of the aeroelastic rotor analysis, which is the center of a wind turbine simulation model, analysis of the gimbal subsystem; and listings of the variables, constants, and equations used in the simulation

Background of the Analysis of a Fully-Scalable Digital Fractional Clock Divider

It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm. It draws out the limits encountered by the existing implementation for both FPGA and VLSI realizations. A rather unconventional adoption of the carry-save representation combined with a soft-threshold comparison is proposed to circumvent these limitations. The resulting design is described and evaluated. Mathematically appealing results on the quality of the approximation achieved by this approach are presented. The underlying proofs and technical details are provided in the appendix

Detecting relative amplitude of IR signals with active sensors and its application to a positioning system

Nowadays, there is an increasing interest in smart systems, e.g., smart metering or smart spaces, for which active sensing plays an important role. In such systems, the sample or environment to be measured is irradiated with a signal (acoustic, infrared, radio‐frequency…) and some of their features are determined from the transmitted or reflected part of the original signal. In this work, infrared (IR) signals are emitted from different sources (four in this case) and received by a unique quadrature angular diversity aperture (QADA) sensor. A code division multiple access (CDMA) technique is used to deal with the simultaneous transmission of all the signals and their separation (depending on the source) at the receiver’s processing stage. Furthermore, the use of correlation techniques allows the receiver to determine the amount of energy received from each transmitter, by quantifying the main correlation peaks. This technique can be used in any system requiring active sensing; in the particular case of the IR positioning system presented here, the relative amplitudes of those peaks are used to determine the central incidence point of the light from each emitter on the QADA. The proposal tackles the typical phenomena, such as distortions caused by the transducer impulse response, the near‐far effect in CDMA‐based systems, multipath transmissions, the correlation degradation from non‐coherent demodulations, etc. Finally, for each emitter, the angle of incidence on the QADA receiveris estimated, assuming that it is on a horizontal plane, although with any rotation on the vertical axis Z. With the estimated angles and the known positions of the LED emitters, the position (x, y, z) of the receiver is determined. The system is validated at different positions in a volume of 3 × 3 × 3.4 m3 obtaining average errors of 7.1, 5.4, and 47.3 cm in the X, Y and Z axes, respectively.Agencia Estatal de InvestigaciónUniversidad de AlcaláJunta de Comunidades de Castilla-La Manch

An object-based codesign methodology.

The research into Codesign of Hardware and Software stems from the development of embedded systems, on which various systems restrictions are imposed. Typical restrictions can be the overall time (latency) to complete an assigned function and the space/power limits within the system. Although software can be used to undertake most tasks in an embedded system, ASIC (Application Specific Integrated Circuits) hardware components sometimes have to be recruited to meet the system constraints. Designing the restricted embedded system with both software and hardware components in it involves the analysis of not only individual hardware/software components but also their mutual influences. Using co-design principles, the approach is to consider both hardware and software from a coherent viewpoint.This thesis presents the results from our research project in the area of Codesign of Hardware and Software. In this project, we investigated previously published codesign approaches and their methodological supports. The investigation has identified shortcomings and problems with the existing codesign methodologies. A new object-based codesign approach (Co-PARSE) is thus developed in this project, which is supported by successive phases, guidelines, and techniques. This methodology offers a coherent design framework for real-time embedded systems and incorporates the criteria of system performance and hardware cost. Tools have been developed to facilitate the use of the methodology. Within the methodology, a high-level system modeling and specification approach has been developed and formalised in the Co-BSL (Codesign Behavior Specification Language). The means of transforming Co-BSL specifications to C and VHDL implementations is defined, and a library of VHDL components provided. The thesis documents the partitioning approach taken within the methodology and proposes a new multi-layered bus architecture as a basis for more flexible and efficient implementations. A means of simulating the performance characteristics of this architecture under different configurations is provided, and examples of simulation results are presented. A new embedded system (the Radio Data Computing System) is designed and simulated in the Co-PARSE methodology and simulation results analysed. The thesis concludes with an evaluation of the work carried out in the project and proposals for extending the results obtained in future research.The major contributions reported in this thesis can be summarised as follows. First, the unified system specification means has been designed, which is embodied in the Co-BSL. It captures overall dynamic aspects and performance constraints in the system under development. This high-level specification language is independent of implementation and does not bias the designer towards the use of hardware or software components at this early stage. Second, within Co-PARSE, the target architecture of the system under development has been exploited to improve the system performance and at the same time to reduce hardware cost. This novel concept has been realised by the introduction of an asynchronous bus protocol and the multi-layer bus communication structure. Third, in order to evaluate the strength and practicability of the Co-PARSE methodology, an extensive case study has been carried out. The new RDC (Radio Dada Computing) System has been designed in the proposed codesign approach. Codesign phases are subsequently applied and the guidelines and tools that are specially developed in support of the methodology are fully utilized

GPS Satellite Kinematic Relative Positioning: Analyzing and Improving the Functional Mathematical Model Using Wavelets

Although GPS kinematic relative positioning can provide high accuracy, GPS observables, like any other kind of measurement, are not free of errors. Indeed, they have several kinds of errors. In this paper, we show how to construct a functional mathematical model within the context of a Kalman Filter in order to eliminate most of these errors. Furthermore, we discuss how the multipath effect, a kind of error not modeled in the functional model, can be corrected using the proposed wavelet method. The behavior of the double difference functional model in the kinematic mode is also demonstrated and analyzed aiming to provide better insight into the problem. The results obtained from the multipath experiments were very promising and are presented here