Power consumption optimization and delay based on ant colony algorithm in network-on-chip

With a further increase of the number of on-chip devices, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new NoC structure to solve the interconnection of an on-chip device. For the purpose of improving the performance of a network-on-chip without a significant increase in power consumption, the paper proposes a network-on-chip that selects NoC (Network-On-Chip) platform with 2-dimension mesh as the carrier and incorporates communication power consumption and delay into a unified cost function. The paper uses ant colony optimization for the realization of NoC map facing power consumption and delay potential. The experiment indicates that in comparison with a random map, single objective optimization can separately account for (30%~47%) and (20%~39%) of communication power consumption and execution time, and joint objective optimization can further excavate the potential of time dimension in a mapping scheme dominated by the power

Reliability aware NoC router architecture using input channel buffer sharing

To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both dynamic virtual channel allocations and the rational sharing among the buffers of different input channels. In particular, in the case of failure in routers, the virtual channels of routers surrounding the faulty routers can be totally recaptured and reassigned to other input ports. Moreover, our proposed RAVC router isolates the faulty router from occupying network bandwidth. Experimental result shows that proposed micro-architecture provides 7.1 % and 3.1 % average latency decrease under uniform and transpose traffic pattern. Considering the existence of failures in routers of on-chip network, RAVC provides 28 % and 16 % decrease in the average packet latency under the uniform and transpose traffic pattern respectively

Towards scalable, energy-efficient, bus-based on-chip networks

Journal ArticleIt is expected that future on-chip networks for many-core processors will impose huge overheads in terms of energy, delay, complexity, verification effort, and area. There is a common belief that the bandwidth necessary for future applications can only be provided by employing packet-switched networks with complex routers and a scalable directory-based coherence protocol. We posit that such a scheme might likely be overkill in a well designed system in addition to being expensive in terms of power because of a large number of power-hungry routers. We show that bus-based networks with snooping protocols can significantly lower energy consumption and simplify network/ protocol design and verification, with no loss in performance. We achieve these characteristics by dividing the chip into multiple segments, each having its own broadcast bus, with these buses further connected by a central bus. This helps eliminate expensive routers, but suffers from the energy overhead of long wires. We propose the use of multiple Bloom filters to effectively track data presence in the cache and restrict bus broadcasts to a subset of segments, significantly reducing energy consumption. We further show that the use of OS page coloring helps maximize locality and improves the effectiveness of the Bloom filters. We also employ low-swing wiring to further reduce the energy overheads of the links. Performance can also be improved at relatively low costs by utilizing more of the abundant metal budgets on-chip and employing multiple address-interleaved buses rather than multiple routers. Thus, with the combination of all the above innovations, we extend the scalability of buses and believe that buses can be a viable and attractive option for future on-chip networks. We show energy reductions of up to 31X on average compared to many state-of-the-art packet switched networks

ideal: Inter-router dual-function energy and area-efficient links for network-on-chip (noc) architectures

ABSTRACT Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power and area constraints. Research into the optimization of NoCs has shown that a reduction in the number of buffers in the NoC routers reduces the power and area overhead but degrades the network performance. In this paper, we propose iDEAL, a low-power area-efficient NoC architecture by reducing the number of buffers within the router. To overcome the performance degradation caused by the reduced buffer size, we propose to use adaptive dual-function links capable of data transmission as well as data storage when required. Simulation results for the proposed architecture show that reducing the router buffer size in half and using the adaptive dualfunction links achieves nearly 40% savings in buffer power, 30% savings in overall network power and about 41% savings in the router area, with only a marginal 1-3% drop in performance. Moreover, the performance in iDEAL can be further improved by aggressive and speculative flow control techniques

Performance Analysis of Different Interconnect Networks for Network on Chip

Nowadays, every electronic system, ranging from a small mobile phone to a satellite sent into space, has a System-on-Chip (SoC). SoCs have undergone rapid evolution and are still progressing at a swift pace. Due to explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate and hence, the SoCs today have become communication-centric and shared bus system and crossbar system were fail to performed communication in side SoC. Interconnection networks offer an alternate solution to this communication paradigm and are becoming persistent in SoC. A NoC based interconnect network is a well-organized and efficiently use of limited communication channel while maintaining low packet latency, high saturation throughput, high communication bandwidth amongst different IPs core with a minimum area and low power-dissipation. In this thesis we present details performance analysis of four interconnect network mesh, torus, fat tree and butterfly in term of latency and throughput under uniform, tornado, neighbour, bit reversal and bit complement traffic using cycle accurate simulator. We also implement NoC interconnect networks on FPGA and see the effect of NoC parameters(FDW,FBD,VC) on FPGA, and validate their performance through FPGA synthesis . We found that the FDW and buffer depth have the great effect on FPGA resources, Virtual Channels (VCs) with all NoC parameter have considerably effect on buffer size and routing and logic requirements at NoC. We also analysis all interconnect networks in term of power and area at 65 nm technology by using synopsis tool. We found that butterfly interconnect network has highest power and Area efficient interconnect network but it will suffer heavily degradation on performance at high load so fat tree network is efficient network among all interconnect network

Savior: A Reliable Fault Resilient Router Architecture for Network-on-Chip

[EN] The router plays an important role in communication among different processing cores in on-chip networks. Technology scaling on one hand has enabled the designers to integrate multiple processing components on a single chip; on the other hand, it becomes the reason for faults. A generic router consists of the buffers and pipeline stages. A single fault may result in an undesirable situation of degraded performance or a whole chip may stop working. Therefore, it is necessary to provide permanent fault tolerance to all the components of the router. In this paper, we propose a mechanism that can tolerate permanent faults that occur in the router. We exploit the fault-tolerant techniques of resource sharing and paring between components for the input port unit and routing computation (RC) unit, the resource borrowing for virtual channel allocator (VA) and multiple paths for switch allocator (SA) and crossbar (XB). The experimental results and analysis show that the proposed mechanism enhances the reliability of the router architecture towards permanent faults at the cost of 29% area overhead. The proposed router architecture achieves the highest Silicon Protection Factor (SPF) metric, which is 24.4 as compared to the state-of-the-art fault-tolerant architectures. It incurs an increase in latency for SPLASH2 and PARSEC benchmark traffics, which is minimal as compared to the baseline router.This work was supported by the Spanish 'Ministerio de Ciencia Innovacion y Universidades' and FEDER program in the framework of the 'Proyectos de I+D d Generacion de Conocimiento del Programa Estatal de Generacion de Conocimiento y Fortalecimiento Cientifico y Tecnologico del Sistema de I+D+i, Subprograma Estatal de Generacion de Conocimiento' (ref: PGC2018-095747-B-I00).Hussain, A.; Irfan, M.; Baloch, NK.; Draz, U.; Ali, T.; Glowacz, A.; Dunai, L.... (2020). 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Wireless Channel Modeling For Networks On Chips

The advent of integrated circuit (chip) multiprocessors (CMPs) combined with the continuous reduction in device physical size (technology scaling) to the sub-nanometer regime will result in an exponential increase in the number of processing cores that can be integrated within a single chip. Today’s CMPs already support tens to low hundreds of cores and both industry and academic roadmaps project that future chips will have thousands of cores. Therefore, while there are open questions on how to harness the computing power offered by CMPs, the design of power-efficient and compact on-chip interconnection networks that connects cores, caches and memory controllers has become imperative for sustaining the performance of CMPs. As the limited scalability of bus-based networks degrades performance by reducing data rates and increasing latency, the Network-on-Chip (NoC) design paradigm has gained momentum, where a network of routers and links connects all the cores. However, power consumption of NoCs is a significant challenge that should be addressed to capitalize on the scaling advantages of multicores. Also, improvements in metal wire characteristics will no longer satisfy the power and performance requirements of on-chip communication. One approach to continue the performance improvements is to integrate new emerging technologies into the electronic design flow such as wireless/RF technologies, since they provide unique advantages that make them desirable in a NoC environment. First, wireless technologies are ubiquitous and offer a wide range of options in communication, and there exists a vast body of knowledge for the design and implementation of wireless chipsets using RF-CMOS technology. Second, wireless communication, unlike wired transmission, can be omnidirectional, which can facilitate one-hop unicast, multicast, and broadcast communication that can result in a reduction in power consumption while allowing for faster communication. Third, wireless communication can increase the communication data rate by the combination of Frequency Division Multiplexing (FDM) and Time Division Multiplexing (TDM) (and in the future, potentially spatial division multiplexing (SDM)). Therefore, Wireless NoC (WiNoC) interconnects have recently emerged as a viable solution to mitigate power concerns in the short to medium term while still providing competitive performance metrics, i.e., low power consumption, tens of Gbps data rates, and minimal circuit area (or volume) within the chip. Worth noting is that wireless links are not envisioned as replacing all wired links, but rather as augmenting the wired interconnection network. In this dissertation, we employ simulations in HFSS from Ansys® to present accurate wireless channel models for a realistic WiNoC environment. We investigate the performance of these models with different types of narrowband and wideband antennas. This entails estimation of the scattering parameters for the channels between multiple antenna elements in the WiNoC, from which we derive channel transfer functions and channel impulse responses. Using these results, we can estimate the throughput of the various WiNoC links, and this allows us to design effective multiple access (MA) schemes via FDM and TDM. For these MA schemes, we provide estimates of maximal throughput. To further the feasibility study, we investigate the performance of a simple binary transmission scheme--On-Off Keying (OOK)--through the resulting dispersive channels, which can facilitate one-hop unicast, multicast, and broadcast communication that can result in a reduction in power consumption while allowing for faster communication. Our investigation of the performance of On-Off Keying modulation (OOK) also includes an analytical expression for bit error ratio (BER) that can be evaluated numerically. This enables us to provide the equalization requirements needed to achieve our target BERs. Finally, we provide recommendations for WiNoC design and future tasks related to this research