Design for Power and Area Efficient Approximate Multipliers

Multimedia and image processing applications, may tolerate errors in calculations but still generate meaningful and beneficial results. This work deals with a high speed approximate multiplier with TDM tree and carry prediction circuit. The modified multiplier utilizes an optimised TDM carry save tree which reduces the device utilization on FPGA as well as the combinational path delay and power consumption. The proposed design is analyzed using the simulation and implementation results on Xilinx Spartan 3E family

Implementation Of ALU sing Low Power Full Adder

This paper is resolved to structure a quick Arithmetic Logic Unit. We as a whole understand that, ALU is a module which can perform math and method of reasoning exercises. The speed of ALU essentially depends on the speed of the Multiplier. This paper demonstrates a strategy called, "Vedic Mathematics" for organizing the multiplier that is fast when diverged from various multipliers reliant on logical strategies that have been for all intents and purposes for a long time. Here, a quick 32x32 piece multiplier is organized and inspected which relies upon the Vedic science instrument. The proposed methodology is capable and snappy, wherein the planning incorporates the vertical and crossed growth of perspective Vedic math. Within multiplier is implemented using Vedic-Wallace structure for quick utilization. The case of the last result is gotten by using Brent-Kung snake for fast figuring’s with less zone use. The foreseen Vedic multiplier is coded in a High-level Digital Language (VHDL) trailed by synthetization using an EDA mechanical assembly, XilinxISE14.5. The proposed ALU can perform three different math and eight particular lucid assignments at quick. The major focus of this paper is to grow the speed of the multiplier and to reduce the delay, and region of the hardware

HLStool: Una herramienta de Síntesis de Alto Nivel para el aprendizaje del estudiante en asignaturas de ATC

La utilización de herramientas de Síntesis de Alto Nivel (SAN) es una práctica habitual en las empresas dedicadas al diseño de circuitos. El principal beneficio de estas herramientas se basa en la reducción del “tiempo de lanzamiento al mercado”, ya que permiten evaluar múltiples soluciones en un tiempo reducido. En esta contribución, se propone el uso de una herramienta de síntesis altamente visual y amigable que contenga los algoritmos clásicos para enseñar al alumno las técnicas básicas de SAN, y adicionalmente familiarizarle con el método de trabajo de las compañías de diseño de circuitos. Con esta contribución se propone ofrecer una formación más completa a los futuros graduados que cursen asignaturas del área de la Arquitectura y Tecnología de Computadores.The use of High-Level Synthesis (HLS) tools is a common practice in circuit design companies. The main benefit of these tools consists of diminishing time to market, as they provide multiple solutions to explore in a reduced amount of time. In this paper we propose the use of a highly visual synthesis tool, which implements the classic algorithms to teach students the basic HLS concepts and to get them closer to the companies’ methodology. In this way, Computer Architecture and Technology related subjects will offer a more complete programme to the future graduates.Universidad de Granada: Departamento de Arquitectura y Tecnología de Computadores; Vicerrectorado para la Garantía de la Calidad

High level synthesis of RDF queries for graph analytics

In this paper we present a set of techniques that enable the synthesis of efficient custom accelerators for memory intensive, irregular applications. To address the challenges of irregular applications (large memory footprint, unpredictable fine-grained data accesses, and high synchronization intensity), and exploit their opportunities (thread level parallelism, memory level parallelism), we propose a novel accelerator design that employs an adaptive and Distributed Controller (DC) architecture, and a Memory Interface Controller (MIC) that supports concurrent and atomic memory operations on a multi-ported/multi-banked shared memory. Among the multitude of algorithms that may benefit from our solution, we focus on the acceleration of graph analytics applications and, in particular, on the synthesis of SPARQL queries on Resource Description Framework (RDF) databases. We achieve this objective by incorporating the synthesis techniques into Bambu, an Open Source high-level synthesis tools, and interfacing it with GEMS, the Graph database Engine for Multithreaded Systems. The GEMS' front-end generates optimized C implementations of the input queries, modeled as graph pattern matching algorithms, which are then automatically synthesized by Bambu. We validate our approach by synthesizing several SPARQL queries from the Lehigh University Benchmark (LUBM)

Sistema domótico distribuido para controlar el riego y el aire acondicionado en el hogar

Este trabajo presenta el proyecto SEDomotics, realizado en la asignatura Sistemas Empotrados Distribuidos, perteneciente a la titulación del Máster en Ingeniería Informática de la Universidad Complutense de Madrid. En este trabajo se describe e implementa una plataforma de control domótico de los sistemas de riego y aire acondicionado en el hogar, utilizando para ello dos placas Arduino y una Raspberry Pi como servidor. Además de capturar los datos en tiempo real, el sistema es capaz de almacenar un histórico con dichos datos.This work presents the SEDomotics project, developed in the Distributed Embedded Systems subject, allocated within the Computer Science Master, which is taught in the Universidad Complutense de Madrid. This work describes and implements a distributed domotic system for the irrigation and air conditioner at home, using for this two Arduino boards and a Raspberry Pi as a server. In addition to capturing real time data, the system is capable of storing a record with that data.Universidad de Granada: Departamento de Arquitectura y Tecnología de Computadores; Vicerrectorado para la Garantía de la Calidad

Bomberman modo multijugador

Este trabajo presenta el proyecto Bomberman, realizado en la asignatura Sistemas Empotrados Distribuidos, perteneciente a la titulación del Máster en Ingeniería Informática de la Universidad Complutense de Madrid. En este trabajo se describe e implementa una adaptación del conocido juego Bomberman en modo multijugador (dos jugadores). En esta versión los dos jugadores tratarán de salir de un laberinto o derrotar a su contrincante para ganar. Este proyecto utiliza dos placas de desarrollo S3CEV40 representado a cada jugador, una Raspberry Pi 2, dos cables hembra-hembra de 9 pines y dos adaptadores a 9 pines-USB para conectar cada cable desde cada placa S3CEV40 a la Raspberry.This paper presents the Bomberman project, carried out in the Distributed Embedded Systems subject, which belongs to the Computer Science Master that is taught at the Complutense University of Madrid. This work describes and implements an adaptation of the well-known Bomberman game in multiplayer mode (for two players). In this version, the two players will try to escape from a labyrinth or to destroy his opponent to win. This project use two S3CEV40 boards to represent the players, a Raspberry Pi 2, two female-to-female 9 pin cables and two 9 pins-to-USB adapters to connect each board to the Raspberry.Universidad de Granada: Departamento de Arquitectura y Tecnología de Computadores; Vicerrectorado para la Garantía de la Calidad

Distributed multi-agent Load Frequency Control for a Large-scale Power System Optimized by Grey Wolf Optimizer

This paper aims to design an optimal distributed multi-agent controller for load frequency control and optimal power flow purposes. The controller parameters are optimized using Grey Wolf Optimization (GWO) algorithm. The designed optimal distributed controller is employed for load frequency control in the IEEE 30-bus test system with six generators. The controller of each generator is considered as one agent. The controllers of agents are implemented in a distributed manner that is control rule of each agent depends on the agents’ own state and the states of their neighbors. Three other types of controllers including centralized controller, decentralized controller, and optimal centralized controller are considered for comparison. The performances of decentralized and distributed controllers are compared with two centralized controllers. In the optimal centralized controller and optimal distributed controller, the objective function is considered to achieve the objective of load frequency control as well as minimize power generation. Simulation results using MATLAB/SIMULINK show that although there is no global information of system in the optimal distributed controller, it has suitably reduced the frequency deviation. Meanwhile the power is optimally generated in the three scenarios of load increasing, load reduction and generator outage

Clasificador completo de células sanguíneas mediante una FPGA de bajo coste, MATLAB y SIMULINK

Actualmente la creación de algoritmos para FPGA tiene un auge considerable gracias a las prestaciones que presentan estos chips para el procesamiento de información. Para mejorar la experiencia en el desarrollo de hardware compañías como MathWorks ofrecen herramientas de síntesis de alto nivel para acelerar el proceso de diseño. En el presente trabajo se analizó el uso de Matlab y Simulink, así como toolbox, enfocados al desarrollo de hardware. Para este análisis se crearon dos casos de estudio para el reconocimiento de células en imágenes de microscopía utilizando redes neuronales. Para cada caso se implementaron modelos basados en el algoritmo DCT, pero empleando diferentes estrategias de extracción de características. Una vez generados los modelos se utilizó el entorno de co-simulación FPGA in-the-loop ofrecido por Simulink para ejecutar los modelos directamente en la FPGA. Se analizaron y presentaron los resultados obtenidos por precisión y por tiempos de ejecución. Adicionalmente se realizan comparaciones entre los modelos generados y su contraparte en software con el fin de validar el grado de mejora obtenido en los tiempos de ejecución con uso de hardware para la aceleración de cómputo