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Noise shaping Asynchronous SAR ADC based time to digital converter
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin
A 24-GHz SiGe Phased-Array ReceiverâLO Phase-Shifting Approach
A local-oscillator phase-shifting approach is introduced to implement a fully integrated 24-GHz phased-array receiver using an SiGe technology. Sixteen phases of the local oscillator are generated in one oscillator core, resulting in a raw beam-forming accuracy of 4 bits. These phases are distributed to all eight receiving paths of the array by a symmetric network. The appropriate phase for each path is selected using high-frequency analog multiplexers. The raw beam-steering resolution of the array is better than 10 [degrees] for a forward-looking angle, while the array spatial selectivity, without any amplitude correction, is better than 20 dB. The overall gain of the array is 61 dB, while the array improves the input signal-to-noise ratio by 9 dB
Basics of RF electronics
RF electronics deals with the generation, acquisition and manipulation of
high-frequency signals. In particle accelerators signals of this kind are
abundant, especially in the RF and beam diagnostics systems. In modern machines
the complexity of the electronics assemblies dedicated to RF manipulation, beam
diagnostics, and feedbacks is continuously increasing, following the demands
for improvement of accelerator performance. However, these systems, and in
particular their front-ends and back-ends, still rely on well-established basic
hardware components and techniques, while down-converted and acquired signals
are digitally processed exploiting the rapidly growing computational capability
offered by the available technology. This lecture reviews the operational
principles of the basic building blocks used for the treatment of
high-frequency signals. Devices such as mixers, phase and amplitude detectors,
modulators, filters, switches, directional couplers, oscillators, amplifiers,
attenuators, and others are described in terms of equivalent circuits,
scattering matrices, transfer functions; typical performance of commercially
available models is presented. Owing to the breadth of the subject, this review
is necessarily synthetic and non-exhaustive. Readers interested in the
architecture of complete systems making use of the described components and
devoted to generation and manipulation of the signals driving RF power plants
and cavities may refer to the CAS lectures on Low-Level RF.Comment: 36 pages, contribution to the CAS - CERN Accelerator School:
Specialised Course on RF for Accelerators; 8 - 17 Jun 2010, Ebeltoft, Denmar
Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops
This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL. The phase noise that is generated by the thermal noise in the oscillator and loop components is calculated. The power dissipation is estimated, focusing on the required dynamic power. The absolute PLL output jitter is calculated, and the optimum PLL bandwidth that gives minimum jitter is derived. It is shown that, with a steep enough input reference clock, this minimum jitter is independent of the reference frequency and output frequency for a given PLL power budget. Based on these insights, a benchmark FOM for PLL designs is proposed
Practical quantum realization of the ampere from the electron charge
One major change of the future revision of the International System of Units
(SI) is a new definition of the ampere based on the elementary charge \emph{e}.
Replacing the former definition based on Amp\`ere's force law will allow one to
fully benefit from quantum physics to realize the ampere. However, a quantum
realization of the ampere from \emph{e}, accurate to within in
relative value and fulfilling traceability needs, is still missing despite many
efforts have been spent for the development of single-electron tunneling
devices. Starting again with Ohm's law, applied here in a quantum circuit
combining the quantum Hall resistance and Josephson voltage standards with a
superconducting cryogenic amplifier, we report on a practical and universal
programmable quantum current generator. We demonstrate that currents generated
in the milliampere range are quantized in terms of
( is the Josephson frequency) with a measurement uncertainty of
. This new quantum current source, able to deliver such accurate
currents down to the microampere range, can greatly improve the current
measurement traceability, as demonstrated with the calibrations of digital
ammeters. Beyond, it opens the way to further developments in metrology and in
fundamental physics, such as a quantum multimeter or new accurate comparisons
to single electron pumps.Comment: 15 pages, 4 figure
Suppression of line voltage related distortion in current controlled grid connected inverters
The influence of selected control strategies on the level
of low-order current harmonic distortion generated by an inverter
connected to a distorted grid is investigated through a combination
of theoretical and experimental studies. A detailed theoretical
analysis, based on the concept of harmonic impedance, establishes
the suitability of inductor current feedback versus output
current feedback with respect to inverter power quality. Experimental
results, obtained from a purpose-built 500-W, three-level,
half-bridge inverter with an L-C-L output filter, verify the efficacy of inductor current as the feedback variable, yielding an
output current total harmonic distortion (THD) some 29% lower
than that achieved using output current feedback. A feed-forward
grid voltage disturbance rejection scheme is proposed as a means to
further reduce the level of low-order current harmonic distortion.
Results obtained from an inverter with inductor current feedback
and optimized feed-forward disturbance rejection show a THD of
just 3% at full-load, representing an improvement of some 53% on
the same inverter with output current feedback and no feed-forward
compensation. Significant improvements in THD were also
achieved across the entire load range. It is concluded that the use
of inductor current feedback and feed-forward voltage disturbance
rejection represent costâeffect mechanisms for achieving improved
output current quality
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