Spur-reduction techniques for PLLs using sub-sampling phase detection

A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the sampler to the VCO. The 2.2GHz PLL in 0.18-μm CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.\u

Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the\ud proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 m CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is 80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is 121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3 ps rms

Time-Mode Analog Circuit Design for Nanometric Technologies

Rapid scaling in technology has introduced new challenges in the realm of traditional analog design. Scaling of supply voltage directly impacts the available voltage-dynamic-range. On the other hand, nanometric technologies with fT in the hundreds of GHz range open opportunities for time-resolution-based signal processing. With reduced available voltage-dynamic-range and improved timing resolution, it is more convenient to devise analog circuits whose performance depends on edge-timing precision rather than voltage levels. Thus, instead of representing the data/information in the voltage-mode, as a difference between two node voltages, it should be represented in time-mode as a time-difference between two rising and/or falling edges. This dissertation addresses the feasibility of employing time-mode analog circuit design in different applications. Specifically: 1) Time-mode-based quanitzer and feedback DAC of SigmaDelta ADC. 2) Time-mode-based low-THD 10MHz oscillator, 3) A Spur-Frequency Boosting PLL with -74dBc Reference-Spur Rejection in 90nm Digital CMOS. In the first project, a new architectural solution is proposed to replace the DAC and the quantizer by a Time-to-Digital converter. The architecture has been fabricated in 65nm and shows that this technology node is capable of achieving a time-matching of 800fs which has never been reported. In addition, a competitive figure-of-merit is achieved. In the low-THD oscillator, I proposed a new architectural solution for synthesizing a highly-linear sinusoidal signal using a novel harmonic rejection approach. The chip is fabricated in 130nm technology and shows an outstanding performance compared to the state of the art. The designed consumes 80% less power; consumes less area; provides much higher amplitude while being composed of purely digital circuits and passive elements. Last but not least, the spur-frequency boosting PLL employs a novel technique that eliminates the reference spurs. Instead of adding additional filtering at the reference frequency, the spur frequency is boosted to higher frequency which is, naturally, has higher filtering effects. The prototype is fabricated in 90nm digital CMOS and proved to provide the lowest normalized reference spurs ever reported

Design of High-Speed CMOS Clock Generation and Data Recovery Circuits

摘要 隨著CMOS製程的進步以及對高速資料傳輸的需求增加，較以往利用到更多頻寬的新規格大量增加且對於高效能類比電路的要求亦與日俱增。在這些電路設計中，歷史悠久的鎖相迴路與其高速應用扮演很重要的角色。雖然相關的電路技巧已發展多年，我們仍然需要新的系統架構及電路技巧來克服與日俱增的電路速度限制。 因此在這本論文裡，我們專注在應用於高速無線及有線系統的鎖相系統設計，其中包括時脈產生及資料回復電路。我們提出了數種系統架構及電路技巧來紓解現今高速CMOS傳送接收機設計的瓶頸。 首先，一個有著自動追蹤能力的數位充電泵校正技巧被提出，其可應用於傳統的鎖相系統中。我們使用了0.18微米 CMOS 製程來製作一個5GHz的頻率合成器來驗證此校正技巧。量測到的輸出邊頻在使用此技巧後在5.2GHz可被壓抑5.35dB. 而所有量測到的輸出邊頻在整個工作頻率範圍內都小於-68.5dBc. 最終量測到相位雜訊在1MHz的頻率間隔下為-110dBc/Hz 。 接著，一個可應用於超寬頻系統中的全頻域頻率合成器在0.18微米 CMOS 製程中被實現。藉由使用一個四相位輸出的除三電路及一個兩級的單邊頻混頻器，所有因單邊混頻而產生的非理想邊頻都至少比主輸出頻率小35dB。整個電路的核心面積為1.5 mm2而整體消耗功率為160mW。 之後我們使用0.18微米 CMOS 製程製作了一個使用閘式數位控制振盪器的10Gb/s 無電感突發式時脈資料回復電路。其中我們使用了一組數位頻率校正架構來減少功率及晶片面積的消耗。 此突發式時脈資料回復電路的有效晶片面積為0.16mm2且從1.8伏的電源供應器消耗36mW。量測到的均方根擾動及峰對峰擾動分別為8.5ps及42.7ps。 在有了突發式時脈資料回復電路的基本知識後，我們將呈現一10Gb/s的時脈資料回復電路，其有著較高的擾動容忍能力。藉由使用一組以閘式數位控制振盪器為基底的相位偵測器，此電路達成了較傳統時脈資料回復電路還寬的線性區域且其擾動容忍能力也增為兩倍，然而其擾動轉移函數並未被影響。此原型電路使用0.13微米 CMOS 製程製作且從1.5伏的電源供應器消耗60mW。其有效晶片面積為0.36mm2。量測結果顯示此時脈資料回復電路在一10Gb/s 的27-1 PRBS輸入下，其均方根擾動及峰對峰擾動分別為0.96ps及7.11ps。最終，我們將為此論文作出結論。ABSTRACT With the progress of the CMOS technologies and the increasing demand for high-speed data communications, new specifications utilizing wider bandwidth than before spawns and the needs for high-performance analog circuits augment as well. The long-standing phase-locked loop (PLL) and its high-speed applications play major roles in these designs. Though relating techniques for PLL have prospered for years, new system architectures and circuit topologies are still desired to overcome the ever-increasing speed limitation. Hence, in this dissertation we focus on the design and application of phase-locked systems for high-speed wireless or wire-line applications, including clock generation and data recovery circuits. Several system architectures and circuit topologies are proposed to alleviate the design bottleneck on high-speed CMOS transceivers. First, a digital technique with auto-tracking ability is presented to calibrate the current mismatch of the charge pump in phase-locked systems. A 5GHz frequency synthesizer is used to justify the proposed calibration technique. It has been has been implemented in 0.18µm CMOS. The measured output spur is suppressed by 5.35dB at 5.2GHz after the calibration circuits are active. The measured output spur levels are less than -68.5 dBc throughout the whole output frequency range. The measured phase noise is -110dBc/Hz at an offset frequency of 1MHz. Next, a 14-band frequency synthesizer for ultra-wideband (UWB) applications has been implemented in 0.18µm CMOS. The unwanted spurs due to frequency mixing are at least –35dB lower than the output carriers by using a quadrature divide-by-3 circuit and a two-stage single-sideband mixer. The core circuit area is 1.5 mm2 and total power consumption is 160mW. Hereafter, a 10Gbps inductorless burst-mode clock and data recovery (BMCDR) circuit using a gated digital-controlled oscillator has been fabricated in 0.18µm CMOS. The digitally frequency-calibrated architecture is adopted to save the power consumption and chip area. The CDR circuit occupies an active area of 0.16mm2 and draws 36mW from a 1.8V supply. The measured rms jitter and peak-to-peak jitter is 8.5ps and 42.7ps, respectively. With the knowledge of BMCDR circuits, a jitter-tolerance-enhanced 10Gb/s clock and data recovery (CDR) circuit is presented. By using a gated-digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector achieves a wide linear range and its jitter tolerance is enhanced by a factor of 2 without sacrificing the jitter transfer. The prototype chip has been fabricated in 0.13µm CMOS and consumes 60mW from a 1.5V supply. It occupies an active area of 0.36mm2. Measurements on the testchip demonstrate an rms jitter of 0.96ps and a peak-to-peak jitter of 7.11ps with a 27-1 PRBS. Finally, we conclude this dissertation.1. Introduction 1 1.1 MOTIVATION 1 1.2 INTRODUCTION TO PHASE-LOCKED SYSTEMS 2 1.2.1 Phase-locked loop 2 1.2.2 Frequency synthesizer and clock generator 3 1.2.3 Clock-and-data recovery circuit 4 1.3 DISSERTATION ORGANIZATION 6 2. A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems 9 2.1 INTRODUCTION 10 2.2 DIGITAL CALIBRATION TECHNIQUE 11 2.3 CIRCUIT DESCRIPTION 16 2.3.1 Switched-delay PFD 17 2.3.2 4-bit digital-controlled CP 18 2.3.3 Voltage-controlled oscillator (VCO) and dividers 19 2.3.4 Lock detector (LD) and bang-bang phase detector (BBPD) 20 2.3.5 4-bit SAR controller 22 2.4 EXPERIMENTAL RESULTS 27 3. A 14-band Frequency Synthesizer for MB-OFDM UWB Application 31 3.1 INTRODUCTION 31 3.2 SYNTHESIZER ARCHITECTURE 32 3.3 CIRCUIT DETAILS 36 3.3.1 Ring oscillators and frequency doublers 36 3.3.2 Quadrature divide-by-3 circuit 37 3.3.3 3-band SSB mixer 38 3.3.4 8-band SSB mixer 39 3.4 MEASUREMENT RESULTS 41 4. A 10Gbps Inductorless Digitally Frequency-Calibrated Burst-Mode CDR Circuit in 0.18µm CMOS 45 4.1 INTRODUCTION 46 4.2 GATED DIGITAL-CONTROLLED OSCILLATORS 48 4.3 DIGITALLY FREQUENCY-CALIBRATED BURST-MODE CDR 52 4.3.1 The digitally frequency-calibrated burst-mode CDR circuit 52 4.3.2 The tolerable frequency deviating range for the GDCO 55 4.3.3 Design considerations for the DFCL 59 4.4 EXPERIMENTAL RESULTS 61 5. A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector 67 5.1 INTRODUCTION 68 5.2 PROPOSED JITTER-TOLERANCE-ENHANCING TECHNIQUE 69 5.3 ARCHITECTURE OF THE JITTER-TOLERANCE-ENHANCED CDR 72 5.3.1. CDR Architecture 72 5.3.2 Jitter transfer of the proposed CDR 75 5.3.3 Jitter tolerance of the proposed CDR 77 5.4 BUILDING BLOCKS OF THE PROPOSED CDR 78 5.4.1 Gated digital-controlled oscillator (GDCO) 78 5.4.2 Voltage-controlled oscillator (VCO) 82 5.4.3 Phase-Frequency Detector and CP (PFD and CP) 83 5.4.4 D flip-flops and dividers 84 5.5 EXPERIMENTAL RESULTS 85 6. Conclusions 9