Channel selection requirements for Bluetooth receivers using a simple demodulation algorithm

In our Software Defined Radio (SDR) project we combine two different types of standards, Bluetooth and HiperLAN/2, on one common hardware platform. SDR system research aims at the design, implementation and deployment of flexible radio systems that are reprogrammable and re-configurable by software. Goal of our project is to generate knowledge about designing the front end of an SDR system (from the antenna signal to the channel bit stream) where especially an approach from both analog and digital perspective is essential. This paper discusses the channel selection requirements for the Bluetooth standard. The standard specifications specify only the power level of the interferers, the power level of the wanted signal and the maximum allowed Bit Error Rate (BER). In order to build a radio front-end, one has to know the required (channel) suppression of these interferers. From [1] it is known that the required SNR for a Bluetooth demodulator is 21 dB, but by which value should interferers be suppressed? This paper will validate if the SNR value needs to be used for the suppression of adjacent channels. In order to answer this question a simulation model of a Bluetooth radio front-end is built

Channel Selection requirements for Bluetooth receivers using a simple demodulation algorithm

In our Software Defined Radio (SDR) project we combine two different types of standards, Bluetooth and HiperLAN/2, on one common hardware platform. SDR system research aims at the design, implementation and deployment of flexible radio systems that are reprogrammable and re-configurable by software. Goal of our project is to generate knowledge about designing the front end of an SDR system (from the antenna signal to the channel bit stream) where especially an approach from both analog and digital perspective is essential. This paper discusses the channel selection requirements for the Bluetooth standard. The standard specifications specify only the power level of the interferers, the power level of the wanted signal and the maximum allowed Bit Error Rate (BER). In order to build a radio front-end, one has to know the required (channel) suppression of these interferers. From [1] it is known that the required SNR for a Bluetooth demodulator is 21 dB, but by which value should interferers be suppressed? This paper will validate if the SNR value needs to be used for the suppression of adjacent channels. In order to answer this question a simulation model of a Bluetooth radio front-end is built

Analog-to-digital interface design in wireless receivers

As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues. A zero-crossing demodulator ADI is designed in the 0.35µm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modification improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a configurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25µm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode. In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications

Optimisation of Bluetooth wireless personal area networks

In recent years there has been a marked growth in the use of wireless cellular telephones, PCs and the Internet. This proliferation of information technology has hastened the advent of wireless networks which aim to increase the accessibility and reach of communications devices. Ambient Intelligence (Ami) is a vision of the future of computing in which all kinds of everyday objects will contain intelligence. To be effective, Ami requires Ubiquitous Computing and Communication, the latter being enabled by wireless networking. The IEEE's 802.11 task group has developed a series of radio based replacements for the familiar wired ethernet LAN. At the same time another IEEE standards task group, 802.15, together with a number of industry consortia, has introduced a new level of wireless networking based upon short range, ad-hoc connections. Currently, the most significant of these new Wireless Personal Area Network (WPAN) standards is Bluetooth, one of the first of the enabling technologies of Ami to be commercially available. Bluetooth operates in the internationally unlicensed Industrial, Scientific and Medical (ISM) band at 2.4 GHz. unfortunately, this spectrum is particularly crowded. It is also used by: WiFi (IEEE 802.11); a new WPAN standard called Zig- Bee; many types of simple devices such as garage door openers; and is polluted by unintentional radiators. The success of a radio specification for ubiquitous wireless communications is, therefore, dependant upon a robust tolerance to high levels of electromagnetic noise. This thesis addresses the optimisation of low power WPANs in this context, with particular reference to the physical layer radio specification of the Bluetooth system

An Analogue Front-End Architecture for Software Defined Radio

A Software Defined Radio (SDR) is a radio receiver and/or transmitter, whose characteristics can to a large extent be defined by software. Thus, an SDR can receive and/or transmit a wide variety of signals, supporting many different standards. In our research, we currently focus on a demonstrator that is able to receive both Bluetooth and HiperLAN/2. This helps us to identify problems associated with SDR, and will provide a test-bed for possible solutions to these problems. The two standards differ significantly in characteristics like frequency band, signal bandwidth and modulation type. Combining two different standards in one receiver appears to pose new design challenges. For example, in the wide frequency range that we want to receive, many strong signals\ud may exist. This leads to severe linearity requirements for wideband receivers. This paper describes some receiver architectures. One\ud design has been selected. This receiver has been built, and some measurement results are included

An Analogue Front-End Test-Bed for Software Defined Radio

A Software Defined Radio (SDR) is a radio receiver and/or transmitter, whose characteristics can to a large extent be defined by software. Thus, an SDR can receive and/or transmit a wide variety of signals, supporting many different standards. In our research, we currently focus on a demonstrator that is able to receive both Bluetooth and HiperLAN/2. This helps us to identify problems associated with SDR, and will provide a test-bed for possible solutions to these problems. The two standards differ significantly in characteristics like frequency band, signal bandwidth and modulation type. Combining two different standards in one receiver appears to pose new design challenges. For example, in the wide frequency range that we want to receive, many strong signals\ud may exist. This leads to severe linearity requirements for wideband receivers. This paper describes some receiver architectures. One\ud design has been selected. This receiver has been built, and some measurement results are included

A characterization of the performance of Bluetooth 2.x + EDR technology in noisy environments

Bluetooth (BT) is by far the most popular shortrange technology for the development of wireless personal area networks and body area networks. Nowadays, BT 2.0 and 2.1 ? EDR are the most extended and implemented versions of BT standard. This article presents an analytical model that computes the packet delay of transmissions that utilize this version of BT in noisy environments. The model, which takes into account the packet retransmissions caused by noise, is particularized to calculate the mean packet delay as a function of the signal-to-noise ratio for the different enhanced data rates provided by BT 2.0 and 2.1 specifications. Thus, the model permits evaluating the efficiency of using these enhanced rates in the presence of a certain noise level.Ministerio de Ciencia e Innovación TEC2009-13763-C02-01Ministerio de Ciencia e Innovación TEC2013-42711-

Efficient and Interference-Resilient Wireless Connectivity for IoT Applications

With the coming of age of the Internet of Things (IoT), demand on ultra-low power (ULP) and low-cost radios will continue to boost tremendously. The Bluetooth-Low-energy (BLE) standard provides a low power solution to connect IoT nodes with mobile devices, however, the power of maintaining a connection with a reasonable latency remains the limiting factor in defining the lifetime of event-driven BLE devices. BLE radio power consumption is in the milliwatt range and can be duty cycled for average powers around 30μW, but at the expense of long latency. Furthermore, wireless transceivers traditionally perform local oscillator (LO) calibration using an external crystal oscillator (XTAL) that adds significant size and cost to a system. Removing the XTAL enables a true single-chip radio, but an alternate means for calibrating the LO is required. Innovations in both the system architecture and circuits implementation are essential for the design of truly ubiquitous receivers for IoT applications. This research presents two porotypes as back-channel BLE receivers, which have lower power consumption while still being robust in the presents of interference and able to receive back-channel message from BLE compliant transmitters. In addition, the first crystal-less transmitter with symmetric over-the-air clock recovery compliant with the BLE standard using a GFSK-Modulated BLE Packet is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162942/1/abdulalg_1.pd

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007