Built-in-self-test of RF front-end circuitry

Fuelled by the ever increasing demand for wireless products and the advent of deep submicron CMOS, RF ICs have become fairly commonplace in the semiconductor market. This has given rise to a new breed of Systems-On-Chip (SOCs) with RF front-ends tightly integrated along with digital, analog and mixed signal circuitry. However, the reliability of the integrated RF front-end continues to be a matter of significant concern and considerable research. A major challenge to the reliability of RF ICs is the fact that their performance is also severely degraded by wide tolerances in on-chip passives and package parasitics, in addition to process related faults. Due to the absence of contact based testing solutions in embedded RF SOCs (because the very act of probing may affect the performance of the RF circuit), coupled with the presence of very few test access nodes, a Built In Self Test approach (BiST) may prove to be the most efficient test scheme. However due to the associated challenges, a comprehensive and low-overhead BiST methodology for on-chip testing of RF ICs has not yet been reported in literature. In the current work, an approach to RF self-test that has hitherto been unexplored both in literature and in the commercial arena is proposed. A sensitive current monitor has been used to extract variations in the supply current drawn by the circuit-under-test (CUT). These variations are then processed in time and frequency domain to develop signatures. The acquired signatures can then be mapped to specific behavioral anomalies and the locations of these anomalies. The CUT is first excited by simple test inputs that can be generated on-chip. The current monitor extracts the corresponding variations in the supply current of the CUT, thereby creating signatures that map to various performance metrics of the circuit. These signatures can then be post-processed by low overhead on-chip circuitry and converted into an accessible form. To be successful in the RF domain any BIST architecture must be minimally invasive, reliable, offer good fault coverage and present low real estate and power overheads. The current-based self-test approach successfully addresses all these concerns. The technique has been applied to RF Low Noise Amplifiers, Mixers and Voltage Controlled Oscillators. The circuitry and post-processing techniques have also been demonstrated in silicon (using the IBM 0.25 micron RF CMOS process). The entire self-test of the RF front-end can be accomplished with a total test time of approximately 30µs, which is several orders of magnitude better than existing commercial test schemes

Dynamic input match correction in R.F. low noise amplifiers

An R.F. circuit that recognizes its faults, and then corrects its performance in real-time has been the holy-grail of RFIC design. This work presents, for the first time, a complete architecture and successful implementation of such a circuit. It is the first step towards the grand vision of fault-free, package independent, integrated R.F. Front End circuitry. The performance of R.F. front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input. These inductances have wide tolerances and are difficult to co-design for. A novel methodology, which overcomes current obstacles plaguing such an objective, is proposed wherein the affected performance metric of the circuit is quantified, and the appropriate design parameter is modified in real-time, thus enabling self-correction. This proof of concept is demonstrated by designing a cascode LNA and the complete self-correction circuit in IBM 0.25 µm CMOS RF process. The self-correction circuitry ascertains the input match frequency of the circuit by measuring its performance and determines the frequency interval by which it needs to be shifted to restore it to the desired value. It then feeds back a digital word to the LNA which adaptively corrects its input-match. It offers the additional flexibility of using different packages for the front-end since it renders the circuitry independent of package parasitics, by re-calibrating the input match on-the-fly. The circuitry presented in this work offers the advantages of low power, robustness, absence of DSP cores or processors, reduction in design cycle times, guaranteed optimal performance under varying conditions and fast correction times (less than 30 µs)

Fault-tolerant design of RF front-end circuits

The continuing trends of scaling in the CMOS industry have, inevitably, been accompanied by an ever-increasing array of process faults and fabrication complexities. The relentless march towards miniaturization and massive integration, in addition to increasing operating frequencies has resulted in increasing concerns about the reliability of integrated RF front-ends. Coupled with rising cost per chip, the fault-tolerant paradigm has become pertinent in the RFIC domain. Two main reasons have contributed to the fact that fault-tolerant solutions for circuits that operate in the GHz domain have not been realized so far. First, GHz signals are extremely sensitive to higher-order effects such as stray pick-ups, interference, package & on-chip parasitics, etc. Secondly, the use of passives, especially inductors, in the feedback path poses huge area overheads, in addition to a slew of instability problems due to wide variations and soft faults. Hence traditional fault-tolerance methods used in digital and low frequency analog circuits cannot be applied in the RF domain. This work presents a unique methodology to achieve fault-tolerance in RF circuits through dynamic sensing and on-chip self-correction, along with the development of robust algorithms. This technique is minimally intrusive and is transparent during \u27normal\u27 use of the circuit. It is characterized by low area and power overheads, does not need any off-chip computing or DSP cores, and is characterized by self-correction times in the range of a few hundreds of microseconds. It compares very well with existing commercial RF test solutions that use DSP cores and require hundreds of milliseconds. The methodology is demonstrated on a LNA, since it is critical for the performance of the entire front-end. It is validated with simulation and fabrication results of the system designed in IBM 0.25 µm CMOS 6RF process

Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology

Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version

Real-time swath width sensing for grain combines

The practice of precision agriculture is utilized in grain production to make decisions to lower costs and increase profits. To make these decisions, an accurate determination of yield is required at each position within the field. Current yield measurement incorporates yield monitors and Global Positioning System (GPS) receivers to calculate yield from grain flow and position. The primary problem encountered is a varying width of cut due to operator error or when cutting point rows near ends and edges of a field. To more accurately measure yield, a method for measuring harvest cutting width has been developed. The non-intrusive sensing system consists of infrared emitter-detector pairs mounted along the length of the combine header reel. Each sensor element emits a beam of light into the crop canopy and detects the signal as it is reflected by plants. The emitted signal modulated pulses of light that are detected when a crop is present. Zero pulses from a detector indicate no plants were present; a higher number indicates plants were in the field of view. The sensors are active once each reel revolution. Software analysis was developed and performed to assemble the recorded numbers of pulses counted into a data matrix and to use this information to predict other locations that should have detected plants. The software then determined the measured swath width. The sensing system was tested on a combine harvesting with a 12 ft header. Field testing was then performed in production soybeans. Actual detection by the sensors occurred at only 16% of the locations in the harvest area where plants were present. However, the software analysis routines increased the locations plants were present to 62%. Data analysis routines based on knowledge of the crop canopy increased accuracy significantly. Refinements are necessary in the sensor elements to increase their sensing range and to improve the location at which sensors are sampled. Increasing the detection by the sensors allows the software to more accurately determine the harvested width. Future testing should focus on maximizing the efficiency and detection rate of the sensors under varying crop conditions

Solutions pour l'auto-adaptation des systèmes sans fil

The current demand on ubiquitous connectivity imposes stringent requirements on the fabrication of Radio-Frequency (RF) circuits. Designs are consequently transferred to the most advanced CMOS technologies that were initially introduced to improve digital performance. In addition, as technology scales down, RF circuits are more and more susceptible to a lot of variations during their lifetime, as manufacturing process variability, temperature, environmental conditions, aging… As a result, the usual worst-case circuit design is leading to sub-optimal conditions, in terms of power and/or performance most of the time for the circuit. In order to counteract these variations, increasing the performances and also reduce power consumption, adaptation strategies must be put in place.More importantly, the fabrication process introduces more and more performance variability, which can have a dramatic impact on the fabrication yield. That is why RF designs are not easily fabricated in the most advanced CMOS technologies, as 32nm or 22nm nodes for instance. In this context, the performances of RF circuits need to be calibrated after fabrication so as to take these variations into account and recover yield loss.This thesis work is presenting on a post-fabrication calibration technique for RF circuits. This technique is performed during production testing with minimum extra cost, which is critical since the cost of test can be comparable to the cost of fabrication concerning RF circuits and cannot be further raised. Calibration is enabled by equipping the circuit with tuning knobs and sensors. Optimal tuning knob identification is achieved in one-shot based on a single test step that involves measuring the sensor outputs once. For this purpose, we rely on variation-aware sensors which provide measurements that remain invariant under tuning knob changes. As an auxiliary benefit, the variation-aware sensors are non-intrusive and totally transparent to the circuit.Our proposed methodology has first been demonstrated with simulation data with an RF power amplifier as a case study. Afterwards, a silicon demonstrator has then been fabricated in a 65nm technology in order to fully demonstrate the methodology. The fabricated dataset of circuits is extracted from typical and corner wafers. This feature is very important since corner circuits are the worst design cases and therefore the most difficult to calibrate. In our case, corner circuits represent more than the two third of the overall dataset and the calibration can still be proven. In details, fabrication yield based on 3 sigma performance specifications is increased from 21% to 93%. This is a major performance of the technique, knowing that worst case circuits are very rare in industrial fabrication.La demande courante de connectivité instantanée impose un cahier des charges très strict sur la fabrication des circuits Radio-Fréquences (RF). Les circuits doivent donc être transférées vers les technologies les plus avancées, initialement introduites pour augmenter les performances des circuits purement numériques. De plus, les circuits RF sont soumis à de plus en plus de variations et cette sensibilité s’accroît avec l’avancées des technologies. Ces variations sont par exemple les variations du procédé de fabrication, la température, l’environnement, le vieillissement… Par conséquent, la méthode classique de conception de circuits “pire-cas” conduit à une utilisation non-optimale du circuit dans la vaste majorité des conditions, en termes de performances et/ou de consommation. Ces variations doivent donc être compensées, en utilisant des techniques d’adaptation.De manière plus importante encore, le procédé de fabrication des circuits introduit de plus en plus de variabilité dans les performances des circuits, ce qui a un impact important sur le rendement de fabrication des circuits. Pour cette raison, les circuits RF sont difficilement fabriqués dans les technologies CMOS les plus avancées comme les nœuds 32nm ou 22nm. Dans ce contexte, les performances des circuits RF doivent êtres calibrées après fabrication pour prendre en compte ces variations et retrouver un haut rendement de fabrication.Ce travail de these présente une méthode de calibration post-fabrication pour les circuits RF. Cette méthodologie est appliquée pendant le test de production en ajoutant un minimum de coût, ce qui est un point essentiel car le coût du test est aujourd’hui déjà comparable au coût de fabrication d’un circuit RF et ne peut être augmenté d’avantage. Par ailleurs, la puissance consommée est aussi prise en compte pour que l’impact de la calibration sur la consommation soit minimisé. La calibration est rendue possible en équipant le circuit avec des nœuds de réglages et des capteurs. L’identification de la valeur de réglage optimale du circuit est obtenue en un seul coup, en testant les performances RF une seule et unique fois. Cela est possible grâce à l’utilisation de capteurs de variations du procédé de fabrication qui sont invariants par rapport aux changements des nœuds de réglage. Un autre benefice de l’utilisation de ces capteurs de variation sont non-intrusifs et donc totalement transparents pour le circuit sous test. La technique de calibration a été démontrée sur un amplificateur de puissance RF utilisé comme cas d’étude. Une première preuve de concept est développée en utilisant des résultats de simulation.Un démonstrateur en silicium a ensuite été fabriqué en technologie 65nm pour entièrement démontrer le concept de calibration. L’ensemble des puces fabriquées a été extrait de trois types de wafer différents, avec des transistors aux performances lentes, typiques et rapides. Cette caractéristique est très importante car elle nous permet de considérer des cas de procédé de fabrication extrêmes qui sont les plus difficiles à calibrer. Dans notre cas, ces circuits représentent plus des deux tiers des puces à disposition et nous pouvons quand même prouver notre concept de calibration. Dans le détails, le rendement de fabrication passe de 21% avant calibration à plus de 93% après avoir appliqué notre méthodologie. Cela constitue une performance majeure de notre méthodologie car les circuits extrêmes sont très rares dans une fabrication industrielle

Household Electrical Power Meter Using Embedded Rfid With Wireless Sensor Network Platform

Smart monitoring utility electrical power meter plays an important role in the energy awareness scheme. The aim of this study is to develop a machine-to-machine (M2M) communication by embedding an active RFID technology with wireless mesh sensor network (WMSN) platform with heterogeneous data transfer to monitor and identify the household electrical consumption. A household electrical power meter is designed with chosen Zigbee-Pro as a RF transceiver module with WSN functionalities to communicate between RFID tag to the RFID reader wirelessly. The development of this project involves three main parts in the proposed RFID communication system which consists of: the EPRFID (embedded RFID module with household electrical power meter), reader and application software at a work station. The EPRFID module is designed to take power supply from a household electric power meter with the introduction of power management circuit developed inside the proposed module. It comprises of voltage and current sensors which is functioning to precisely sense the actual status of the resident electrical power consumption from the appliance loads. Then, the data signal is directly transferred to the central processing unit (CPU) to precisely calculate the current power consumption. The CPU is the central part to effectively communicate and command all defined operations. The real time clock is readily available to generate the local real time clock. It is combined into the memory module package which used to minute the total accumulated power. Simultaneously, the display unit shows the monitored information data such as local time, current, voltage and power values. Lastly, the application software at a personal computer (PC) was designed by using the Microsoft Visual C# software. It shows the performances of received information data from the end meter devices such as tag ID, time sent, receive, delay, accumulated power, RSSI and amount of received bytes. In this research, the EPRFID prototype was intensively examined as follows: the voltage and current calibration versus the distance ranges; the transmitted power calibration; energy analysis; energy tradeoffs based on measured dc characteristics; anti collision performance; radiation pattern; maximum read range; tag collection and latency delay time; throughput evaluation. The experimental results indicated that the proposed EPRFID prototype successfully worked wirelessly with tolerable power consumption is within a range of 1.61 W to 1.69 W. This model is to facilitate some daily life processes, saving time, and reduces the operating cost because of the reduction in the manpower requirement and error in information system that can be omitted through humans. Thus, improving the M2M communication can provide higher reliability on the communication system because the current development will focus on local control strategies. In addition, this study can be guidelines to the electrical power utility company and consumers for alternatives in electrical consumption billings in the future

MiliPoint: A Point Cloud Dataset for mmWave Radar

Millimetre-wave (mmWave) radar has emerged as an attractive and cost-effective alternative for human activity sensing compared to traditional camera-based systems. mmWave radars are also non-intrusive, providing better protection for user privacy. However, as a Radio Frequency (RF) based technology, mmWave radars rely on capturing reflected signals from objects, making them more prone to noise compared to cameras. This raises an intriguing question for the deep learning community: Can we develop more effective point set-based deep learning methods for such attractive sensors? To answer this question, our work, termed MiliPoint, delves into this idea by providing a large-scale, open dataset for the community to explore how mmWave radars can be utilised for human activity recognition. Moreover, MiliPoint stands out as it is larger in size than existing datasets, has more diverse human actions represented, and encompasses all three key tasks in human activity recognition. We have also established a range of point-based deep neural networks such as DGCNN, PointNet++ and PointTransformer, on MiliPoint, which can serve to set the ground baseline for further development