Horn fragments of the Halpern-Shoham Interval Temporal Logic

We investigate the satisfiability problem for Horn fragments of the Halpern-Shoham interval temporal logic depending on the type (box or diamond) of the interval modal operators, the type of the underlying linear order (discrete or dense), and the type of semantics for the interval relations (reflexive or irreflexive). For example, we show that satisfiability of Horn formulas with diamonds is undecidable for any type of linear orders and semantics. On the contrary, satisfiability of Horn formulas with boxes is tractable over both discrete and dense orders under the reflexive semantics and over dense orders under the irreflexive semantics but becomes undecidable over discrete orders under the irreflexive semantics. Satisfiability of binary Horn formulas with both boxes and diamonds is always undecidable under the irreflexive semantics

Studying and Analysing Transactional Memory Using Interval Temporal Logic and AnaTempura

Transactional memory (TM) is a promising lock-free synchronisation technique which offers a high-level abstract parallel programming model for future chip multiprocessor (CMP) systems. Moreover, it adapts the well-established popular paradigm of transactions and thus provides a general and flexible way to allow programs to read and modify disparate memory locations atomically as a single operation. In this thesis, we propose a general framework for validating a TM design, starting from a formal specification into a hardware implementation, with its underpinning theory and refinement. A methodology in this work starts with a high-level and executable specification model for an abstract TM with verification for various correctness conditions of concurrent transactions. This model is constructed within a flexible transition framework that allows verifying correctness of a TM system with animation. Then, we present a formal executable specification for a chip-dual single-cycle MIPS processor with a cache coherence protocol and integrate the provable TM system. Finally, we transform the dual processors with the TM from a high-level description into a Hardware Description Language (VHDL), using some proposed refinement and restriction rules. Interval Temporal Logic (ITL) and its programming language subset AnaTempura are used to build, execute and test the model, since they together provide a powerful framework supporting logical reasoning about time intervals as well as programming and simulation

A compositional framework for hardware/software co-design

We describe a compositional framework, together with its supporting toolset, for hardware/software co-design. Our framework is an integration of a formal approach within a traditional design flow. The formal approach is based on Interval Temporal Logic and its executable subset, Tempura. Refinement is the key element in our framework because it will derive from a single formal specification of the system the software and hardware parts of the implementation, while preserving all properties of the system specification. During refinement simulation is used to choose the appropriate refinement rules, which are applied automatically in the HOL system. The framework is illustrated with two case studies. The work presented is part of a UK collaborative research project between the Software Technology Research Laboratory at the De Montfort University and the Oxford University Computing Laboratory

A Compositional Framework for Hardware/Software Co-Design. Design Autom. for Emb.

Abstract. We describe a compositional framework, together with its supporting toolset, for hardware/software co-design. Our framework is an integration of a formal approach within a traditional design flow. The formal approach is based on Interval Temporal Logic and its executable subset, Tempura. Refinement is the key element in our framework because it will derive from a single formal specification of the system the software and hardware parts of the implementation, while preserving all properties of the system specification. During refinement simulation is used to choose the appropriate refinement rules, which are applied automatically in the HOL system. The framework is illustrated with two case studies. The work presented is part of a UK collaborative research project between the Software Technology Research Laboratory at the De Montfort University and the Oxford University Computing Laboratory

Embedded Systems Design in the UK: Special Issue

Guest Editor Introduction Scientific and commercial interest in the development of systematic and concurrent design techniques for embedded systems have risen significantly in recent years driven by numerous factors including cost, performance and shrinking time-to-market constraints of consumer and automotive electronics. This special issue reflects some of the latest developments and practices in embedded system design in UK universities. The aim of this special issue is to provide a focused and up-to-date coverage of the UK research activities in this dynamic and important field of research. It is hoped that this coverage will provide useful information to the research community as well as opportunities to possible collaboration between UK, Europe and USA universities and industries. This special issue of Design Automation for Embedded Systems includes seven papers describing recent research in hardware-software co-design CAD tools, embedded systems application and formal verification. Some of the papers are extended versions of selected papers from the IEE Workshop on Hardware-Software Co-Design, held in London, December 2000. All papers submitted to the special issue have been thoroughly reviewed and revised before acceptance. The first paper, ? HASoC- Towards a New Method for System-on-a-Chip Development?, by P. Green, M. Edwards, and S. Essa, UMIST, presents a methodology for developing embedded systems targeting SoC implementation, emphasizing reuse of existing hardware and software cores. The second paper, ? A System-based Approach to the Formal Development of Embedded Controllers for a Railway?, by M. Butler, University of Southampton, describes a formal approach to the development of embedded controllers for a railway, starting with a system-level specification. The B method is used as the formal notation and methodology. The next two papers deal with software tools for hardware-software co-design. The third paper, ? A Compositional Framework for Hardware-Software Co-Design?, by A. Cau, R. Hale, J. Dimitrov, H. Zedan, and B. Moszkowski, De Montfort University, and M. Manjunathaiah, and M. Spivey, Oxford University describes a framework, which integrates formal verification with traditional design flow of embedded systems. Two case studies are used to illustrate the presented framework. The fourth paper, ?Synthesizing Energy-Efficient Embedded Systems with LOPOCOS?, by M. Schmitz, B.M. Al-Hashimi, University of Southampton, and P. Eles, Linkoping University, Sweden, introduces a prototype CAD tool, Low Power Co-Synthesis (LOPOCOS), which targets the design of energy-efficient heterogeneous embedded systems containing dynamic voltage scalable (DVS) processors. A number of design examples are given including a real-life example illustrating the capabilities of the tool. The fifth paper, ?Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Co-Design?, by T. Wiangtong, P. Cheung, and W. Luk, Imperial College, provides a systematic comparison between three heuristic search algorithms: genetic algorithms, simulated annealing, and tabu search, for hardware-software partitioning problem, and report on their solutions quality, search time, and how they can be improved. The last two papers address applications of embedded systems. The sixth paper, ? CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications?, by M. Lewis, and L. Brackenbury, University of Manchester, describes an efficient design flow for the development of configurable asynchronous DSP for reduced energy (CADRE), low power IP block intended for digital mobile phone chipsets applications. The last paper, ? Enhanced Image Detection on an ARM Based Embedded System? by J. R. Evans, and T. Arslan, University of Edinburgh, presents the development of a low complexity image recognition technique for automatic optical inspection system targeting an embedded SoC system based on ARM7 target processor. The capabilities of the system are illustrated through practical examples. I would like to sincerely thank all the authors for submitting their papers and the reviewers for keeping up with the very tight schedule that allowed us to complete this special issue as planned in less than a year. Also, I would like to thank Prof. W. Wolf for his invitation to organize this special issue and Kluwer Academic Publishers staff particularly M. de Jongh and C. Knight for helping me with the administration. Bashir Al-Hashimi Guest Editor University of Southampton, U