Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Field-Effect Sensors

This Special Issue focuses on fundamental and applied research on different types of field-effect chemical sensors and biosensors. The topics include device concepts for field-effect sensors, their modeling, and theory as well as fabrication strategies. Field-effect sensors for biomedical analysis, food control, environmental monitoring, and the recording of neuronal and cell-based signals are discussed, among other factors

Low-power Wearable Healthcare Sensors

Advances in technology have produced a range of on-body sensors and smartwatches that can be used to monitor a wearer’s health with the objective to keep the user healthy. However, the real potential of such devices not only lies in monitoring but also in interactive communication with expert-system-based cloud services to offer personalized and real-time healthcare advice that will enable the user to manage their health and, over time, to reduce expensive hospital admissions. To meet this goal, the research challenges for the next generation of wearable healthcare devices include the need to offer a wide range of sensing, computing, communication, and human–computer interaction methods, all within a tiny device with limited resources and electrical power. This Special Issue presents a collection of six papers on a wide range of research developments that highlight the specific challenges in creating the next generation of low-power wearable healthcare sensors

CMOS and SOI CMOS FET-based gas sensors

In recent years, there has been considerable interest in the use of gas/vapour monitors and electronic nose instruments by the environmental, automotive and medical industries. These applications require low cost and low power sensors with high yield and high reproducibility, with an annual prospective market of 1 million pounds. Present device and sensor technologies suffer a major limitation, their incompatibility with a standard silicon CMOS process. These technologies have either operating/annealing temperatures unsuited for MOSFET operation or an inappropriate sensing mechanism. The aim of this research is the development of CMOS compatible gas/vapour sensors, with a low cost of fabrication, high device repeatability and, in the future, transducer sensor amalgamation. Two novel approaches have been applied, utilising bulk CMOS and SOI BiCMOS. The bulk CMOS designs use a MOSFET sensing structure, with an active polymeric gate material, operating at low temperatures (<100°C), based on an array device of four elements, with channel lengths of 10 μm or 5 μm. The SOI designs exploit a MOSFET heater with a chemoresistive or chemFET sensing structure, on a thin membrane formed by the epi-taxial layer. By applying SOI technology, the first use in gas sensor applications, operating temperatures of up to 300 °C can be achieved at a power cost of only 35 mW (simulated). Full characterisation of the bulk CMOS chemFET sensors has been performed using electrochemically deposited (e.g. poly(pyrrole)/BSA)) and composite polymers (e.g. poly(9-vinylcarbazole)) to ethanol and toluene vapour in air. In addition, environmental factors (humidity and temperature) on the response and baseline were investigated. This was carried out using a newly developed flow injection analysis test station, which conditions the test vapour to precise analyte (<15 PPM of toluene) and water concentrations at a fixed temperature (RT to 105°C +- 0.1), with the sensor characterised by either I-V or constant current instrumentation. N-channel chemFET sensors operated at constant current (10 μA) with electrochemically deposited and composite polymers showed sensitivities of up to 1.1 μV/PPM and 4.0 μV/PPM to toluene vapour and to 1.1 μV/PPM and 0.4 μV/PPM for ethanol vapour, respectively, with detection limits of <20 PPM and <100 PPM to toluene and <20 PPM and 10+ PPM to ethanol vapour (limited by baseline noise), respectively. These responses followed either a power law (composite polymers) or a modified Langmuir isotherm model (electrochemically deposited polymers) with analyte concentration. It is proposed that this reaction-rate limited response is due to an alteration in polymers work function by either a partial charge transfer from the analyte or a swelling effect (polymer expansion). Increasing humidity caused, in nearly all cases a reduction in relative baseline, possible by dipole formation at the gate oxide surface. For the response, increasing humidity had no effect on sensors with composite polymers and an increase for sensors with electrochemically-deposited polymers. Higher temperatures caused a reduction in baseline signal, by a thermal expansion of the polymer, and a reduction in response explained by the analyte boiling point model describing a reduction in the bulk solubility of the polymer. Electrical and thermal characterisation of the SOI heaters, fabricated by the MATRA process, has been performed. I-V measurements show a reduction in drain current for a MOSFET after back-etching, by a degradation of the carrier mobility. Dynamic measurement showed a two stage thermal response (dual exponential), as the membrane reaching equilibrium (100-200 ms) followed by the bulk (1-2 s). A temperature coefficient of 8 mW/°C was measured, this was significantly higher than expected from simulations, explained by the membrane being only partially formed. Diode and resistive temperature sensors showed detection limits under 0.1°C and shown to measure a modulated heater output of less than 1°C at frequencies higher than 10Hz. The principal research objectives have been achieved, although further work on the SOI device is required. The results and theories presented in this study should provide a useful contribution to this research area

EUROSENSORS XVII : book of abstracts

Fundação Calouste Gulbenkien (FCG).Fundação para a Ciência e a Tecnologia (FCT)

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

INTEGRATION OF CMOS TECHNOLOGY INTO LAB-ON-CHIP SYSTEMS APPLIED TO THE DEVELOPMENT OF A BIOELECTRONIC NOSE

This work addresses the development of a lab-on-a-chip (LOC) system for olfactory sensing. The method of sensing employed is cell-based, utilizing living cells to sense stimuli that are otherwise not easily sensed using conventional transduction techniques. Cells have evolved over millions of years to be exquisitely sensitive to their environment, with certain types of cells producing electrical signals in response to stimuli. The core device that is introduced here is comprised of living olfactory sensory neurons (OSNs) on top of a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC). This hybrid bioelectronic approach to sensing leverages the sensitivity of OSNs with the electronic signal processing capability of modern ICs. Intimately combining electronics with biology presents a number of unique challenges to integration that arise from the disparate requirements of the two separate domains. Fundamentally the obstacles arise from the facts that electronic devices are designed to work in dry environments while biology requires not only a wet environment, but also one that is precisely controlled and non-toxic. Design and modeling of such heterogeneously integrated systems is complicated by the lack of tools that can address the multiple domains and techniques required for integration, namely IC design, fluidics, packaging, and microfabrication, and cell culture. There also arises the issue of how to handle the vast amount of data that can be generated by such systems, and specifically how to efficiently identify signals of interest and communicate them off-chip. The primary contributions of this work are the development of a new packaging scheme for integration of CMOS ICs into fluidic LOC systems, a methodology for cross-coupled multi-domain iterative modeling of heterogeneously integrated systems, demonstration of a proof-of-concept bioelectronic olfactory sensor, and a novel event-based technique to minimize the bandwidth required to communicate the information contained in bio-potential signals produced by dense arrays of electrically active cells

Ultra-thin silicon technology for tactile sensors

In order to meet the requirements of high performance flexible electronics in fast growing portable consumer electronics, robotics and new fields such as Internet of Things (IoT), new techniques such as electronics based on nanostructures, molecular electronics and quantum electronics have emerged recently. The importance given to the silicon chips with thickness below 50 μm is particularly interesting as this will advance the 3D IC technology as well as open new directions for high-performance flexible electronics. This doctoral thesis focusses on the development of silicon–based ultra-thin chip (UTC) for the next generation flexible electronics. UTCs, on one hand can provide processing speed at par with state-of-the-art CMOS technology, and on the other provide the mechanical flexibility to allow smooth integration on flexible substrates. These development form the motivation behind the work presented in this thesis. As the thickness of any silicon piece decreases, the flexural rigidity decreases. The flexural rigidity is defined as the force couple required to bend a non-rigid structure to a unit curvature, and therefore the flexibility increases. The new approach presented in this thesis for achieving thin silicon exploits existing and well-established silicon infrastructure, process, and design modules. The thin chips of thicknesses ranging between 15 μm – 30 μm, were obtained from processed bulk wafer using anisotropic chemical etching. The thesis also presents thin wafer transfer using two-step transfer printing approach, packaging by lamination or encapsulation between two flexible layerand methods to get the electrical connections out of the chip. The devices realised on the wafer as part of front-end processing, consisted capacitors and transistors, have been tested to analyse the effect of bending on the electrical characteristics. The capacitance of metal-oxide-semiconductor (MOS) capacitors increases by ~5% during bending and similar shift is observed in flatband and threshold voltages. Similarly, the carrier mobility in the channel region of metal-oxide-semiconductor field effect transistor (MOSFET) increases by 9% in tensile bending and decreases by ~5% in compressive bending. The analytical model developed to capture the effect of banding on device performance showed close matching with the experimental results. In order to employ these devices as tactile sensors, two types of piezoelectric materials are investigated, and used in extended gate configuration with the MOSFET. Firstly, a nanocomposite of Poly(vinylidene fluoride-co-trifluoroethylene), P(VDF-TrFE) and barium titanate (BT) was developed. The composite, due to opposite piezo and pyroelectric coefficients of constituents, was able to suppress the sensitivity towards temperature when force and temperature varied together, The sensitivity to force in extended gate configuration was measured to be 630 mV/N, and sensitivity to temperature was 6.57 mV/oC, when it was varied during force application. The process optimisation for sputtering piezoelectric Aluminium Nitride (AlN) was also carried out with many parametric variation. AlN does not require poling to exhibit piezoelectricity and therefore offers an attractive alternative for the piezoelectric layer used in devices such as POSFET (where piezoelectric material is directly deposited over the gate area of MOSFET). The optimised process gave highly orientated columnar structure AlN with piezoelectric coefficient of 5.9 pC/N and when connected in extended gate configuration, a sensitivity (normalised change in drain current per unit force) of 2.65 N-1 was obtained