500mV low-voltage operational amplifier design

With the dramatic increase in the number of transistors on a chip and the increasing needs for battery-powered applications, low-voltage circuit design techniques have been widely studied in recent year. However, these low supply voltage research efforts have been focused mainly on digital circuits, especially on high density memory circuits. Reported success in achieved high performance low voltage operation in analog circuits lags far behind. Recent results have been presented on CMOS low-voltage operational amplifiers, where the supply voltage has been reduced to less than 2.5V in which the complementary input stages were used to keep the gm constant [SI95] [HL85]. Recently, the floating gate MOS transistor has attracted considerable interest as a nonvolatile analog storage device and as a precision analog trim element because it has threshold voltage programming ability [YU93] [RC95].;The particular focus of this work is on implementing very low voltage analog and mixed-signal integrated circuit in a standard CMOS process. As a proof-of-concept vehicle, this work concentrates on the design of very low voltage operational amplifiers in standard CMOS processes. By connecting a DC reference voltage source in series with the gate of all MOS transistors, the equivalent threshold voltage of all transistors can be electrically lowered. This technique makes it possible to decrease the power supply voltage. The DC reference voltage sources are realized by using a switched capacitor charged periodically and switched between the actual circuit and a reference precharge circuit. By extracting the reference voltage source directly from the threshold voltage itself, the threshold voltage variations due to the process and temperature variations can be compensated, since large threshold variations are intolerable for very low threshold voltage applications.;In a proof-of-concept two-stage operational amplifier designed to operate with a single 5OOmV power supply in a standard 2[Mu] process, the tail current is kept the same as in a 3.3V design, thus the key performance parameters are expected to be maintained at reasonable values. The dramatic decrease of the power supply possible with this approach is paralleled with a corresponding reduction in the power dissipation. Simulation results of this 5OOmV operational amplifier show a 7OdB DC gain, 7.8MHz unity gain bandwidth and a 650 phase margin. Power dissipation is reduced by more than 90% from that of the corresponding 3.3V design. Although the specific implementation is focused on the implementation of an operational amplifier with comparable performance parameters to those with larger supply voltage, the dominant applications of this technique are for designing a variety of analog and mixed-signal systems that operate at very low voltages and with low power dissipation

A Radiation hard bandgap reference circuit in a standard 0.13um CMOS Technology

With ongoing CMOS evolution, the gate-oxide thickness steadily decreases, resulting in an increased radiation tolerance of MOS transistors. Combined with special layout techniques, this yields circuits with a high inherent robustness against X-rays and other ionizing radiation. In bandgap voltage references, the dominant radiation-susceptibility is then no longer associated with the MOS transistors, but is dominated by the diodes. This paper gives an analysis of radiation effects in both MOSdevices and diodes and presents a solution to realize a radiation-hard voltage reference circuit in a standard CMOS technology. A demonstrator circuit was implemented in a standard 0.13 m CMOS technology. Measurements show correct operation with supply voltages in the range from 1.4 V down to 0.85 V, a reference voltage of 405 mV 7.5 mV ( = 6mVchip-to-chip statistical spread), and a reference voltage shift of only 1.5 mV (around 0.8%) under irradiation up to 44 Mrad (Si)

Near-Zero-Power Temperature Sensing via Tunneling Currents Through Complementary Metal-Oxide-Semiconductor Transistors.

Temperature sensors are routinely found in devices used to monitor the environment, the human body, industrial equipment, and beyond. In many such applications, the energy available from batteries or the power available from energy harvesters is extremely limited due to limited available volume, and thus the power consumption of sensing should be minimized in order to maximize operational lifetime. Here we present a new method to transduce and digitize temperature at very low power levels. Specifically, two pA current references are generated via small tunneling-current metal-oxide-semiconductor field effect transistors (MOSFETs) that are independent and proportional to temperature, respectively, which are then used to charge digitally-controllable banks of metal-insulator-metal (MIM) capacitors that, via a discrete-time feedback loop that equalizes charging time, digitize temperature directly. The proposed temperature sensor was integrated into a silicon microchip and occupied 0.15 mm2 of area. Four tested microchips were measured to consume only 113 pW with a resolution of 0.21 °C and an inaccuracy of ±1.65 °C, which represents a 628× reduction in power compared to prior-art without a significant reduction in performance

Characterisation of AMS H35 HV-CMOS monolithic active pixel sensor prototypes for HEP applications

Monolithic active pixel sensors produced in High Voltage CMOS (HV-CMOS) technology are being considered for High Energy Physics applications due to the ease of production and the reduced costs. Such technology is especially appealing when large areas to be covered and material budget are concerned. This is the case of the outermost pixel layers of the future ATLAS tracking detector for the HL-LHC. For experiments at hadron colliders, radiation hardness is a key requirement which is not fulfilled by standard CMOS sensor designs that collect charge by diffusion. This issue has been addressed by depleted active pixel sensors in which electronics are embedded into a large deep implantation ensuring uniform charge collection by drift. Very first small prototypes of hybrid depleted active pixel sensors have already shown a radiation hardness compatible with the ATLAS requirements. Nevertheless, to compete with the present hybrid solutions a further reduction in costs achievable by a fully monolithic design is desirable. The H35DEMO is a large electrode full reticle demonstrator chip produced in AMS 350 nm HV-CMOS technology by the collaboration of Karlsruher Institut f\"ur Technologie (KIT), Institut de F\'isica d'Altes Energies (IFAE), University of Liverpool and University of Geneva. It includes two large monolithic pixel matrices which can be operated standalone. One of these two matrices has been characterised at beam test before and after irradiation with protons and neutrons. Results demonstrated the feasibility of producing radiation hard large area fully monolithic pixel sensors in HV-CMOS technology. H35DEMO chips with a substrate resistivity of 200$\Omega$ cm irradiated with neutrons showed a radiation hardness up to a fluence of $10^{15}$n$_{eq}$cm$^{-2}$ with a hit efficiency of about 99% and a noise occupancy lower than $10^{-6}$ hits in a LHC bunch crossing of 25ns at 150V

An Extended CMOS ISFET Model Incorporating the Physical Design Geometry and the Effects on Performance and Offset Variation

This paper presents an extended model for the CMOS-based ion-sensitive field-effect transistor, incorporating design parameters associated with the physical geometry of the device. This can, for the first time, provide a good match between calculated and measured characteristics by taking into account the effects of nonidealities such as threshold voltage variation and sensor noise. The model is evaluated through a number of devices with varying design parameters (chemical sensing area and MOSFET dimensions) fabricated in a commercially available 0.35-µm CMOS technology. Threshold voltage, subthreshold slope, chemical sensitivity, drift, and noise were measured and compared with the simulated results. The first- and second-order effects are analyzed in detail, and it is shown that the sensors' performance was in agreement with the proposed model

A system-on-chip digital pH meter for use in a wireless diagnostic capsule

This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is designed in a modular fashion to facilitate verification and component re-use. The single-chip pH meter can be directly connected to a personal computer, and gives a response of 37 bits/pH, within an operating range of 7 pH units

Dynamic range optimisation of CMOS image sensors dedicated to space applications

Nowadays, CMOS image sensors are widely considered for space applications. Their performances have been significantly enhanced with the use of CIS (CMOS Image Sensor) processes in term of dark current, quantum efficiency and conversion gain. Dynamic Range (DR) remains an important parameter for a lot of applications. Most of the dynamic range limitation of CMOS image sensors comes from the pixel. During work performed in collaboration with EADS Astrium, SUPAERO/CIMI laboratory has studied different ways to improve dynamic range and test structures have been developed to perform analysis and characterisation. A first way to improve dynamic range will be described, consisting in improving the voltage swing at the pixel output. Test vehicles and process modifications made to improve voltage swing will be depicted. We have demonstrated a voltage swing improvement more than 30%. A second way to improve dynamic range is to reduce readout noise A new readout architecture has been developed to perform a correlated double sampling readout. Strong readout noise reduction will be demonstrated by measurements performed on our test vehicle. A third way to improve dynamic range is to control conversion gain value. Indeed, in 3 TMOS pixel structure, dynamic range is related to conversion gain through reset noise which is dependant of photodiode capacitance. Decrease and increase of conversion gain have been performed with different design techniques. A good control of the conversion gain will be demonstrated with variation in the range of 0.05 to 3 of initial conversion gain

Design of a single-chip pH sensor using a conventional 0.6-μm CMOS process

A pH sensor fabricated on a single chip by an unmodified, commercial 0.6-/spl μm CMOS process is presented. The sensor comprises a circuit for making differential measurements between an ion-sensitive field-effect transistor (ISFET) and a reference FET (REFET). The ISFET has a floating-gate structure and uses the silicon nitride passivation layer as a pH-sensitive insulator. As fabricated, it has a large threshold voltage that is postulated to be caused by a trapped charge on the floating gate. Ultraviolet radiation and bulk-substrate biasing is used to permanently modify the threshold voltage so that the ISFET can be used in a battery-operated circuit. A novel post-processing method using a single layer of photoresist is used to define the sensing areas and to provide robust encapsulation for the chip. The complete circuit, operating from a single 3-V supply, provides an output voltage proportional to pH and can be powered down when not required

CMOS detectors for space applications: from R&D to operational program with large volume foundry

Nowadays, CMOS image sensors are widely considered for space applications. The use of CIS (CMOS Image sensor) processes has significantly enhanced their performances such as dark current, quantum efficiency and conversion gain. However, in order to fulfil specific space mission requirements, dedicated research and development work has to be performed to address specific detector performance issues. This is especially the case for dynamic range improvement through output voltage swing optimisation, control of conversion gain and noise reduction. These issues have been addressed in a 0.35μm CIS process, based on a large volume CMOS foundry, by several joint ISAE- EADS Astrium R&D programs. These results have been applied to the development of the visible and near-infrared multi-linear imager for the SENTINEL 2 mission (LEO Earth observation mission for the Global Measurement Environment and Security program). For this high performance multi-linear device, output voltage swing improvement is achieved by process optimisation done in collaboration with foundry. Conversion gain control is also achieved for each spectral band by managing photodiode capacitance. A low noise level at sensor output is reached by the use of an architecture allowing Correlated Double Sampling readout in order to eliminate reset noise (KTC noise). KTC noise elimination reveals noisy pixels due to RTS noise. Optimisation of transistors’s dimensions, taking into account conversion gain constraints, is done to minimise these noisy pixels. Additional features have been also designed: 1) Due to different integration times between spectral bands required by mission, a specific readout mode was developed in order to avoid electrical perturbations during the integration time and readout. This readout mode leads to specific power supply architecture. 2)Post processing steps can be achieved by alignment marks design allowing a very good accuracy. These alignment marks can be used for a black coating deposition between spectral bands (pixel line) in order to minimise straight lighteffects. In conclusion a review of design improvements and performances of the final component is performed