A CMOS dB-linear VGA with pre-distortion compensation for wireless communication applications

Proceedings - IEEE International Symposium on Circuits and Systems1I813-I816PICS

A CMOS DB-linear VGA with DC offset cancellation for direct-conversion receiver

Master'sMASTER OF ENGINEERIN

Design of a variable gain amplifier for an ultrawideband receiver

A fully differential CMOS variable gain amplifier (VGA) has been designed for an ultra-wideband receiver. The VGA comprises of two variable gain stages followed by a post amplifier stage. The interface between the digital control block and the analog VGA is formed by a digital-to-analog converter and an exponential voltage generator. The gain of the VGA varies dB-linearly from 0 to 52 dB with respect to the control voltage. The VGA is operated in open loop with a bandwidth greater than 500 MHz throughout the gain range to cater to the requirements of the ultra-wideband system. The noise-to-power ratio of the VGA is -23.9 dB for 1Vp-p differential input signal in the low gain setting, and the equivalent input referred noise is 1.01 V2 for the high gain setting. All three stages use common mode feedback to fix and stabilize the output DC levels at a particular voltage depending on the input common-mode requirement of the following stage. DC offset cancellation has also been incorporated to minimize the input referred DC offset caused by systematic and random mismatches in the circuit. Compensation schemes to minimize the effects of temperature, supply and process variations have been included in the design. The circuit has been designed in 0.18??m CMOS technology, and the post layout simulations are in good agreement with the schematic simulations

A low power, high dynamic-range, broadband variable gain amplifier for an ultra wideband receiver

A fully differential Complementary Metal-Oxide Semiconductor (CMOS) Variable Gain Amplifier (VGA) consisting of complementary differential pairs with source degeneration, a current gain stage with programmable current mirror, and resistor loads is designed for high frequency and low power communication applications, such as an Ultra Wideband (UWB) receiver system. The gain can be programmed from 0dB to 42dB in 2dB increments with -3dB bandwidth greater than 425MHz for the entire range of gain. The 3rd-order intercept point (IIP3) is above -13.6dBm for 1Vpp differential input and output voltages. These low distortion broadband features benefit from the large linear range of the differential pair with source degeneration and the low impedance internal nodes in the current gain stages. In addition, common-mode feedback is not required because of these low impedance nodes. Due to the power efficient complementary differential pairs in the input stage, power consumption is minimized (9.5mW) for all gain steps. The gain control scheme includes fine tuning (2dB/step) by changing the bias voltage of the proposed programmable current mirror, and coarse tuning (14dB/step) by switching on/off the source degeneration resistors in the differential pairs. A capacitive frequency compensation scheme is used to further extend the VGA bandwidth