Analog integrated circuit design techniques for high-speed signal processing in communications systems

This work presents design techniques for the implementation of high-speed analog integrated circuits for wireless and wireline communications systems. Limitations commonly found in high-speed switched-capacitor (SC) circuits used for intermediate frequency (IF) filters in wireless receivers are explored. A model to analyze the aliasing effects due to periodical non-uniform individual sampling, a technique used in high-Q high-speed SC filters, is presented along with practical expressions that estimate the power of the generated alias components. The results are verified through circuit simulation of a 10.7MHz bandpass SC filter in TSMC 0.35mu-m CMOS technology. Implications on the use of this technique on the design of IF filters are discussed. To improve the speed at which SC networks can operate, a continuous-time common-mode feedback (CMFB) with reduced loading capacitance is proposed. This increases the achievable gain-bandwidth product (GBW) of fully-differential ampli- fiers. The performance of the CMFB is demonstrated in the implementation of a second-order 10.7MHz bandpass SC filter and compared with that of an identical filter using the conventional switched-capacitor CMFB (SC-CMFB). The filter using the continuous-time CMFB reduces the error due to finite GBW and slew rate to less than 1% for clock frequencies up to 72MHz while providing a dynamic range of 59dB and a PSRR- > 22dB. The design of high-speed transversal equalizers for wireline transceivers requires the implementation of broadband delay lines. A delay line based on a third-order linear-phase filter is presented for the implementation of a fractionally-spaced 1Gb/s transversal equalizer. Two topologies for a broadband summing node which enable the placement of the parasitic poles at the output of the transversal equalizer beyond 650MHz are presented. Using these cells, a 5-tap 1Gb/s equalizer was implemented in TSMC 0.35mu-m CMOS technology. The results show a programmable frequency response able to compensate up to 25dB loss at 500MHz. The eye-pattern diagrams at 1Gb/s demonstrate the equalization of 15 meters and 23 meters of CAT5e twistedpair cable, with a vertical eye-opening improvement from 0% (before the equalizer) to 58% (after the equalizer) in the second case. The equalizer consumes 96mW and an area of 630mu-m x 490mu-m

Modelização em MatLab® de interfaces de comunicação de alto débito

Mestrado em Engenharia Electrónica e TelecomunicaçõesNow-a-days, high-speed digital data transmission is under continuous development. The constant increasing on the bitrates has been lead to the need of more sophisticated and complex receivers, systems that provide the recovering of the transmitted data over a dispersive channel that degrades the transmitted signal quality. Therefore, the receiver shall compensate the distortion introduced by the channel as well as synchronize the received signal that in addition to distortion, is also affected by jitter. The distortion derived from the channel is attenuated by means of equalization circuits that offset the channel frequency response at the transmission rate, making it as flat as possible for the desired frequency. On the other hand, the synchronization of the received signal is achieved by means of clock and data recovery circuits that usually recover the clock signal through the data transitions for sampling the received data. The main focus of this thesis concerns the modeling of a data receiver for a high-speed interface. The simulation of the data receiver block implies the modeling of a transmission channel depending on its characteristics. The proposed transmission system, from the transmitter to the output of the data recovery block, includes equalization filters for signal conditioning, of which several distinct architectures are studied. It’s proposed two architectures for the clock and data recovery circuit. The first one is a 2x oversampling clock and data recovery circuit based on a Phase Tracking architecture. The second one, is a 3x oversampling clock and data recovery based on a Blind Sampling architecture. By modeling both of the architectures of the clock and data recovery circuit, it’s intended to analyze the respective jitter tolerance results. It is crucial to know the amount of jitter that can be tolerated by these circuits in order to recover the data with a satisfying bit error ratio. The obtained results show a very close match to the theoretical values, where the 2x and 3x oversampling architecture presents a jitter tolerance of, approximately, 12UI and 23UI respectively for low jitter frequencies.Hoje em dia, a transmissão de dados digital de alto débito binário encontra-se em constante evolução. O contínuo aumento das taxas de transmissão tem vindo a exigir sistemas de receção cada vez mais sofisticados e complexos, que facultem a recuperação dos dados transmitidos ao longo de um canal dispersivo que degrada a qualidade do sinal transmitido. Consequentemente, cabe ao recetor compensar a distorção introduzida pelo canal bem como a sincronização do sinal recebido que, para além de sofrer distorção, vem também afetado por jitter. A distorção introduzida pelo canal é atenuada através de circuitos de igualização, que compensam a resposta em frequência do canal à frequência de transmissão, de maneira a tornar a mesma o mais plana possível para a frequência desejada. Por sua vez, a sincronização do sinal recebido é conseguida através de circuitos de recuperação de dados e relógio, que, geralmente, geram um sinal de relógio a partir das transições do sinal de dados que é posteriormente utilizado para fazer a amostragem dos dados recebidos. O principal foco desta tese incide na modelação de um sistema de receção de dados de uma interface de alta velocidade. A simulação do bloco de receção de dados implica a modelação de um canal de transmissão em função das características do mesmo. O sistema de transmissão proposto, desde o transmissor até à saída do bloco de recuperação de dados, inclui filtros de igualização para acondicionamento de sinal, dos quais várias arquiteturas distintas são estudadas. São propostas duas arquiteturas para o circuito de recuperação de dados e relógio. A primeira trata-se de um circuito de recuperação de dados e relógio com sobre-amostragem 2x, baseado numa arquitetura de Phase Tracking. A segunda arquitetura trata-se de um circuito de recuperação de dados e relógio com sobre-amostragem 3x, baseado num arquitetura Blind Sampling. A análise de resultados da modelação de ambas as arquiteturas do circuito de recuperação de dados e relógio é realizada através da aquisição das respetivas curvas de tolerância de jitter. É fundamental conhecer a quantidade de jitter tolerado por estes circuitos a fim de recuperar os dados com uma probabilidade de erro de bit satisfatória. Os resultados obtidos mostram uma correspondência bastante próxima dos valores teóricos, onde a arquitetura com sobre-amostragem 2x apresenta uma tolerância de jitter de, aproximadamente, 12UI e a arquitetura com sobre-amostragem 3x apresenta uma tolerância de, aproximadamente, 23UI para baixas frequências de jitter

Analog FIR Filter Used for Range-Optimal Pulsed Radar Applications

Matched filter is one of the most critical block in radar applications. With different measured range and relative velocity of a target we will need different bandwidth of the matched filter to maximize the radar signal to noise ratio (SNR). Conventional matched filter designs incorporate surface acoustic wave (SAW) filters. However, it is not inherently tunable and will need multiple SAW filters with to change the bandwidth resulting in costly solutions. In this work, a novel method of implementing the matched filter with an analog FIR filter is proposed. The FIR filter provides a linear phase response which is suitable for radar applications. Analog FIR filters can be implemented in the discrete domain, requiring operational amplifiers, switches and capacitors. In this work, the FIR filter is implemented using a highly programmable operational transconductance amplifier with tunable transconductance gain. The operational amplifiers designed for the filter uses a fully differential source degeneration topology to increase the linearity; also capacitive degeneration was placed to compensate its high frequency response. An active continuous-time common mode feedback (CMFB) circuit is also presented. This circuit presents a much smaller load capacitance to the output of the amplifier, yielding a higher frequency response. To satisfy system specifications a 128-tap FIR system is implemented, which require over 128 amplifiers, 136 unity capacitors of 1pF each and 4760 switches. The functionality of the proposed architecture has been verified through schematic and behavior model simulations. In the simulation, the robustness of the FIR filter to process and temperature variation is also verified. The circuits were designed in the TowerJazz 180nm CMOS technology and fabricated on November 2013

Millimetre-Wave Fibre-Wireless Technologies for 5G Mobile Fronthaul

The unprecedented growth in mobile data traffic, driven primarily by bandwidth rich applications and high definition video is accelerating the development of fifth generation (5G) mobile network. As mobile access network evolves towards centralisation, mobile fronthaul (MFH) architecture becomes essential in providing high capacity, ubiquitous and yet affordable services to subscribers. In order to meet the demand for high data rates in the access, Millimetre-wave (mmWave) has been highlighted as an essential technology in the development of 5G-new radio (5G-NR). In the present MFH architecture which is typically based on common public radio interface (CPRI) protocol, baseband signals are digitised before fibre transmission, featuring high overhead data and stringent synchronisation requirements. A direct application of mmWave 5G-NR to CPRI digital MFH, where signal bandwidth is expected to be up to 1GHz will be challenging, due to the increased complexity of the digitising interface and huge overhead data that will be required for such bandwidth. Alternatively, radio over fibre (RoF) technique can be employed in the transportation of mmWave wireless signals via the MFH link, thereby avoiding the expensive digitisation interface and excessive overhead associated with its implementation. Additionally, mmWave carrier can be realised with the aid of photonic components employed in the RoF link, further reducing the system complexity. However, noise and nonlinearities inherent to analog transmission presents implementation challenges, limiting the system dynamic range. Therefore, it is important to investigate the effects of these impairments in RoF based MFH architecture. This thesis presents extensive research on the impact of noise and nonlinearities on 5G candidate waveforms, in mmWave 5G fibre wireless MFH. Besides orthogonal frequency division multiplexing (OFDM), another radio access technology (RAT) that has received significant attention is filter bank multicarrier (FBMC), particularly due to its high spectral containment and excellent performance in asynchronous transmission. Hence, FBMC waveform is adopted in this work to study the impact of noise and nonlinearities on the mmWave fibre-wireless MFH architecture. Since OFDM is widely deployed and it has been adopted for 5G-NR, the performance of OFDM and FBMC based 5G mmWave RAT in fibre wireless MFH architecture is compared for several implementations and transmission scenarios. To this extent, an end to end transmission testbed is designed and implemented using industry standard VPI Transmission Maker® to investigate five mmWave upconversion techniques. Simulation results show that the impact of noise is higher in FBMC when the signal to-noise (SNR) is low, however, FBMC exhibits better performance compared to OFDM as the SNR improved. More importantly, an evaluation of the contribution of each noise component to the overall system SNR is carried out. It is observed in the investigation that noise contribution from the optical carriers employed in the heterodyne upconversion of intermediate frequency (IF) signals to mmWave frequency dominate the system noise. An adaptive modulation technique is employed to optimise the system throughput based on the received SNR. The throughput of FBMC based system reduced significantly compared to OFDM, due to laser phase noise and chromatic dispersion (CD). Additionally, it is shown that by employing frequency domain averaging technique to enhance the channel estimation (CE), the throughput of FBMC is significantly increased and consequently, a comparable performance is obtained for both waveforms. Furthermore, several coexistence scenarios for multi service transmission are studied, considering OFDM and FBMC based RATs to evaluate the impact inter band interference (IBI), due to power amplifier (PA) nonlinearity on the system performance. The low out of band (OOB) emission in FBMC plays an important role in minimising IBI to adjacent services. Therefore, FBMC requires less guardband in coexistence with multiple services in 5G fibre-wireless MFH. Conversely, OFDM introduced significant OOB to adjacent services requiring large guardband in multi-service coexistence transmission scenario. Finally, a novel transmission scheme is proposed and investigated to simultaneously generate multiple mmWave signals using laser heterodyning mmWave upconversion technique. With appropriate IF and optical frequency plan, several mmWave signals can be realised. Simulation results demonstrate successful simultaneous realisation of 28GHz, 38GHz, and 60GHz mmWave signals

Análisis, simulación y validación de la integridad de la señal en circuito impreso

Debido a la miniaturización de los circuitos electrónicos y a las crecientes velocidades de reloj es mucho más frecuente encontrar problemas de integridad de la señal. Por ello, se ha realizado un análisis de la integridad de la señal de diferentes protocolos de comunicaciones como Automotive Ethernet 1000Base-T1 y USB 2.0, certificando el cumplimiento de los requerimientos propios de cada estándar. Para ello se ha empleado el diagrama de ojo, que es la representación superpuesta de los símbolos de la comunicación de forma que se pueda comprobar que son semejantes entre sí. Además, se ha analizado la presencia de distorsión del ciclo de trabajo e interferencia entre símbolos en el diagrama de ojo de forma gráfica. Por último, se ha realizado una reflectometría en el dominio del tiempo para comprobar la continuidad de la impedancia, de forma que se garantice la inexistencia de reflexiones que puedan comprometer la integridad de la señal