A CMOS Wideband Linear Current Attenuator with Electronically Variable Gain

A CMOS highly linear current attenuator is described. The circuit is suited for both differential and single input currents. The current gain is electronically variable between -1 and +1 by means of two controlling currents. A simple additional circuit is described to obtain a gain that is linearly dependent on a single control current. The circuit can be used as a four-quadrant current multiplier. The current attenuator is realized in a standard 2.5 μm CMOS process using channel lengths of 5 μm. The measured nonlinearity is less than 1% over the entire input current range. Simulations indicate a feasible -3dB bandwidth of over 100 MHz

Bidirectional common-path for 8-to-24 gHz low noise SiGe BiCMOS T/R module core-chip

This thesis is based on the design of an 8-to-24 GHz low noise SiGe BiCMOS Transmitter/Receiver (T/R) Module core-chip in a small area by bidirectional common-path. The next-generation phased array systems require multi-functionality and multi-band operation to form multi-purpose integrated circuits. Wide bandwidth becomes a requirement for the system in various applications, such as electronic warfare, due to leading cheaper and lighter system solutions. Although III-V technologies can satisfy the high-frequency specifications, they are expensive and have a large area. The silicon-based technologies promise high integration capability with low cost, but they sacrifice from the performance to result in desired bandwidth. The presented dissertation targets system and circuit level solutions on the described content. The wideband core-chip utilized a bidirectional common path to surpass the bandwidth limitations. The bidirectionality enhances the bandwidth, noise, gain and area of the transceiver by the removal of the repetitive blocks in the unidirectional common chain. This approach allows succeeding desired bandwidth and compactness without sacrificing from the other high-frequency parameters. The realized core-chip has 31.5 and 32 dB midband gain for the receiver and transmitter respectively, with a + 2.1 dB /GHz of positive slope. Its RMS phase and amplitude errors are lower than 5.60 and 0.8 dB, respectively for 4-bit of resolution. The receiver noise figure is lower than 5 dB for the defined bandwidth while dissipating 112 mW of power in a 5.5 mm2 area. The presented results verify the advantage of the favored architecture and might replace the III-V based counterparts

Architectures, Antennas and Circuits for Millimeter-wave Wireless Full-Duplex Applications

Demand for wireless network capacity keeps growing exponentially every year, as a result a 1000-fold increase in data traffic is projected over the next 10 years in the context of 5G wireless networks. Solutions for delivering the 1000-fold increase in capacity fall into three main categories: deploying smaller cells, allocating more spectrum and improving spectral efficiency of wireless systems. Smaller cells at RF frequencies (1-6GHz) are unlikely to deliver the demanded capacity increase. On the other hand, millimeter-wave spectrum (frequencies over 24GHz) offers wider, multi-GHz channel bandwidths, and therefore has gained significant research interest as one of the most promising solutions to address the data traffic demands of 5G. Another disruptive technology is full-duplex which breaks a century-old assumption in wireless communication, by simultaneous transmission and reception on the same frequency channel. In doing so, full-duplex offers many benefits for wireless networks, including an immediate spectral efficiency improvement in the physical layer. Although FD promises great benefits, self-interference from the transmitter to its own receiver poses a fundamental challenge. The self-interference can be more than a billion times stronger than the desired signal and must be suppressed below the receiver noise floor. In recent years, there has been some research efforts on fully-integrated full-duplex RF transceivers, but mm-wave fully-integrated full-duplex systems, are still in their infancy. This dissertation presents novel architectures, antenna and circuit techniques to merge two exciting technologies, mm-wave and full-duplex, which can potentially offer the dual benefits of wide bandwidths and improved spectral efficiency. To this end, two different antenna interfaces, namely a wideband reconfigurable T/R antenna pair with polarization-based antenna cancellation and an mm-wave fully-integrated magnetic-free non-reciprocal circulator, are presented. The polarization-based antenna cancellation is employed in conjunction with the RF and digital cancellation to design a 60GHz full-duplex 45nm SOI CMOS transceiver with nearly 80dB self-interference suppression. The concepts and prototypes presented in this dissertation have also profound implications for emerging applications such as vehicular radars, 5G small-cell base-stations and virtual reality

A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5° and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB

SiGe BiCMOS ICs for X-Band 7-Bit T/R module with high precision amplitude and phase control

Over the last few decades, phased array radar systems had been utilizing Transmit/Receive (T/R) modules implemented in III-V semiconductor based technologies. However, their high cost, size, weight and low integration capability created a demand for seeking alternative solutions to realize T/R modules. In recent years, SiGe BiCMOS technologies are rapidly growing their popularity in T/R module applications by virtue of meeting high performance requirements with more reduced cost and power dissipation with respect to III-V technologies. The next generation phased array radar systems require a great number of fully integrated, high yield, small-scale and high accuracy T/R modules. In line with these trends, this thesis presents the design and implementation of the first and only 7-Bit X-Band T/R module with high precision amplitude and phase control in the open literature, which is realized in IHP 0.25μ SiGe BiCMOS technology. In the scope of this thesis, sub-blocks of the designed T/R module such as low noise amplifier (LNA), inter-stage amplifier, SiGe Hetero-Junction Bipolar Transistor (HBT) Single- Pole Double-Throw (SPDT) switch and 7-Bit digitally controlled step attenuator are extensively discussed. The designed LNA exhibits Noise Figure (NF) of 1.7 dB, gain of 23 dB, Output Referred Compression Point (OP1dB) of 16 dBm while the inter-stage amplifier gives measured NF of 3 dB, gain of 15 dB and OP1dB of 18 dBm. Moreover, the designed SPDT switch has an Insertion Loss (IL) of 1.7 dB, isolation of 40 dB and OP1dB of 28 dBm. Lastly, the designed 7-Bit SiGe HBT digitally controlled step attenuator demonstrates IL of 8 dB, RMS attenuation error of 0.18 dB, RMS phase error of 2° and OP1dB of 16 dBm. The 7-Bit T/R module is constructed by using the sub-blocks given above, along with a 7- Bit phase shifter (PS) and a power amplifier (PA). Post-layout simulation results show that the designed T/R module exhibits a gain of 38 dB, RMS phase error of 2.6°, RMS amplitude error of 0.82 dB and Rx-Tx isolation of 80 dB across X-Band. The layout of T/R module occupies an area of 11.37 mm2

SOI RF-MEMS Based Variable Attenuator for Millimeter-Wave Applications

The most-attractive feature of microelectromechanical systems (MEMS) technology is that it enables the integration of a whole system on a single chip, leading to positive effects on the performance, reliability and cost. MEMS has made it possible to design IC-compatible radio frequency (RF) devices for wireless and satellite communication systems. Recently, with the advent of 5G, there is a huge market pull towards millimeter-wave devices. Variable attenuators are widely employed for adjusting signal levels in high frequency equipment. RF circuits such as automatic gain control amplifiers, broadband vector modulators, full duplex wireless systems, and radar systems are some of the primary applications of variable attenuators. This thesis describes the development of a millimeter-wave RF MEMS-based variable attenuator implemented by monolithically integrating Coplanar Waveguide (CPW) based hybrid couplers with lateral MEMS varactors on a Silicon–on–Insulator (SOI) substrate. The MEMS varactor features a Chevron type electrothermal actuator that controls the lateral movement of a thick plate, allowing precise change in the capacitive loading on a CPW line leading to a change in isolation between input and output. Electrothermal actuators have been employed in the design instead of electrostatic ones because they can generate relatively larger in-line deflection and force within a small footprint. They also provide the advantage of easy integration with other electrical micro-systems on the same chip, since their fabrication process is compatible with general IC fabrication processes. The development of an efficient and reliable actuator has played an important role in the performance of the proposed design of MEMS variable attenuator. A Thermoreflectance (TR) imaging system is used to acquire the surface temperature profiles of the electrothermal actuator employed in the design, so as to study the temperature distribution, displacement and failure analysis of the Chevron actuator. The 60 GHz variable attenuator was developed using a custom fabrication process on an SOI substrate with a device footprint of 3.8 mm x 3.1 mm. The fabrication process has a high yield due to the high-aspect-ratio single-crystal-silicon structures, which are free from warping, pre-deformation and sticking during the wet etching process. The SOI wafer used has a high resistivity (HR) silicon (Si) handle layer that provides an excellent substrate material for RF communication devices at microwave and millimeter wave frequencies. This low-cost fabrication process provides the flexibility to extend this module and implement more complex RF signal conditioning functions. It is thus an appealing candidate for realizing a wide range of reconfigurable RF devices. The measured RF performance of the 60 GHz variable attenuator shows that the device exhibits attenuation levels (|S21|) ranging from 10 dB to 25 dB over a bandwidth of 4 GHz and a return loss of better than 20 dB. The thesis also presents the design and implementation of a MEMS-based impedance tuner on a Silicon-On-Insulator (SOI) substrate. The tuner is comprised of four varactors monolithically integrated with CPW lines. Chevron actuators control the lateral motion of capacitive thick plates used as contactless lateral MEMS varactors, achieving a capacitance range of 0.19 pF to 0.8 pF. The improvement of the Smith chart coverage is achieved by proper choice of the electrical lengths of the CPW lines and precise control of the lateral motion of the capacitive plates. The measured results demonstrate good impedance matching coverage, with an insertion loss of 2.9 dB. The devices presented in this thesis provide repeatable and reliable operation due to their robust, thick-silicon structures. Therefore, they exhibit relatively low residual stress and are free from stiction and micro-welding problems

Design of broadband vector-sum phase shifters and a phased array demonstrator

Master'sMASTER OF ENGINEERIN

Systematic Comparison of HF CMOS Transconductors

Transconductors are commonly used as active elements in high-frequency (HF) filters, amplifiers, mixers, and oscillators. This paper reviews transconductor design by focusing on the V-I kernel that determines the key transconductor properties. Based on bandwidth considerations, simple V-I kernels with few or no internal nodes are preferred. In a systematic way, virtually all simple kernels published in literature are generated. This is done in two steps: 1) basic 3-terminal transconductors are covered and 2) then five different techniques to combine two of them in a composite V-I kernel. In order to compare transconductors in a fair way, a normalized signal-to-noise ratio (NSNR) is defined. The basic V-I kernels and the five classes of composite V-I kernels are then compared, leading to insight in the key mechanisms that affect NSNR. Symbolic equations are derived to estimate NSNR, while simulations with more advanced MOSFET models verify the results. The results show a strong tradeoff between NSNR and transconductance tuning range. Resistively generated MOSFETs render the best NSNR results and are robust for future technology developments

High resolution, process and temperature compensated phase shifter design using a self generated look up table

Phase resolution is one of the most important parameters in phased array RADAR determining the precision of antenna beam direction and side-lobe level. Especially, in tracking applications the antenna directivity should be high and side-lobe levels must be low in order to abstain from the signals of Jammers. Phase shifters (PS) set phase resolution and directivity; therefore, they are the key components for phased arrays. Among the PS topologies, vector sum type comes forward due to its significant advantage over the other design techniques, in terms of insertion loss, phase error, area and operation bandwidth. However, in design of vector sum type PS, phase and amplitude errors in vectors, and phase insertion of variable gain amplifiers degrades the phase resolution performance of the PS. In order to overcome these issues and improve bit resolution (reduced phase step size and lower phase error while covering 360° phase range), and improve the tolerance on process - temperature variations, the proposed solution in this thesis is the design of a calibration circuit consisting of Power detector (PD), Analog to Digital Converter (ADC) and a Digital Processing Unit (DPU). The main objective of the calibration loop is the generation of a Look up Table (LUT) for target frequency band and at operating temperature. With this technique, the first 7-bit Phase shifter is designed in SiGe- BiCMOS technology, which also has highest fractional bandwidth in literature

Linearization techniques to suppress optical nonlinearity

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.This thesis is shown the implementation of the linearization techniques such as feedforward and pre-distortion feedback linearization to suppress the optical components nonlinearities caused by the fibre and semiconductor optical amplifier (SOA). The simulation verified these two linearization techniques for single tone direct modulation, two tone indirect modulation and ultra wideband input to the optical fibre. These techniques uses the amplified spontaneously emission (ASE) noise reduction in two loops of SOA by a feed-forward and predistortion linearizer and is shown more than 6dB improvement. Also it investigates linearization for the SOA amplifier to cancel out the third order harmonics or inter-modulation distortion (IMD) or four waves mixing. In this project, more than 20 dB reductions is seen in the spectral re-growth caused by the SOA. Amplifier non-linearity becomes more severe with two strong input channels leading to inter-channel distortion which can completely mask a third adjacent channel. The simulations detailed above were performed utilizing optimum settings for the variable gain, phase and delay components in the error correction loop of the feed forward and Predistortion systems and hence represent the ideal situation of a perfect feed-forward and Predistortion system. Therefore it should be consider that complexity of circuit will increase due to amplitude, phase and delay mismatches in practical design. Also it has describe the compatibility of Software Defined Radio with Hybrid Fibre Radio with simulation model of wired optical networks to be used for future research investigation, based on the star and ring topologies for different modulation schemes, and providing the performance for these configurations