A CMOS Broadband Power Amplifier With a Transformer-Based High-Order Output Matching Network

A transformer-based high-order output matching network is proposed for broadband power amplifier design, which provides optimum load impedance for maximum output power within a wide operating frequency range. A design methodology to convert a canonical bandpass network to the proposed matching configuration is also presented in detail. As a design example, a push-pull deep class-AB PA is implemented with a third-order output network in a standard 90 nm CMOS process. The leakage inductances of the on-chip 2:1 transformer are absorbed into the output matching to realize the third-order network with only two inductor footprints for area conservation. The amplifier achieves a 3 dB bandwidth from 5.2 to 13 GHz with +25.2 dBm peak P_sat and 21.6% peak PAE. The EVM for QPSK and 16-QAM signals both with 5 Msample/s are below 3.6% and 5.9% at the output 1 dB compression point. This verifies the PA’s capability of amplifying a narrowband modulated signal whose center-tone can be programmed across a large frequency range. The measured BER for transmitting a truly broadband PRBS signal up to 7.5 Gb/s is less than 10^(-13) , demonstrating the PA’s support for an instantaneous wide operation bandwidth

CMOS Power Amplifier Design Techniques for UWB Communication: A Review

This paper reviews CMOS power amplifier (PA) design techniques in favour of ultra-wideband (UWB) application. The PA circuit design is amongst the most difficult delegation in developing the UWB transmitter due to conditions that must be achieved, including high gain, good input and output matching, efficiency, linearity, low group delay and low power consumption. In order to meet these requirements, many researchers came up with different techniques. Among the techniques used are distributed amplifiers, resistive shunt feedback, RLC matching, shuntshunt feedback, inductive source degeneration, current reuse, shunt peaking, and stagger tuning. Therefore, problems and limitation of UWB CMOS PA and circuit topology are reviewed. A number of works on the UWB CMOS PA from the year 2004 to 2016 are reviewed in this paper. In recent developments, UWB CMOS PA are analysed, hence imparting a comparison of performance criteria based on several different topologies

An Integrated 700–1200 MHz Class-F PA with Tunable Harmonic Terminations in 0.13μm CMOS

A fully integrated class-F power amplifier (PA) with reconfigurable harmonic termination over a wide range of frequencies is presented. Reconfigurability is achieved by utilizing on-chip transformers as part of the output matching network. In addition, a stacked transistor architecture was used to boost the output power. The PA was fabricated in a 0.13- μm CMOS process and packaged in a 20-pin quad flat no-leads package. It was configured to operate at 700, 900, and 1200 MHz with a maximum measured saturated output power of +24.6 dBm with a power-added efficiency of 48.3%. The measured gain was 16.5 dB and was flat over the entire bandwidth. The total chip area, including pads, is 1.5 mm × 1.5 mm

A compact switching mode class-f power amplifier design

Even though there had been extensive research in Switching Mode Power Amplifier design their applications at industry level are quite limited. This is because a Fully-Integrated Switching Mode Power Amplifier using conventional active devices such as Bipolar Junction Transistors (BJT) or Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is challenging due to the inherent design challenges in the Switching Power Amplifier design. A Fully-Integrated Differential Class-F2,3 Power Amplifier design is explored for this Thesis research. This Power Amplifier has a maximum theoretical efficiency of 90.7% but this value is reduced because of the switching nature of the active device, parasitic effects associated with layout and the quality factor of the passive components used. Waveform shaping required for a Class-F Power Amplifier is done using the stray inductances within a non-ideal transformer instead of individual inductors. This techniques effective reduces the foot prints of two inductors for the tuning network design and make a Fully-Integrated solution more practical.M.S

Design of a class-F power amplifier with reconfigurable output harmonic termination in 0.13 µm CMOS

Next generation wireless communication technology requires mobile devices and base stations to support multiband multimode frequencies with higher data rate because of the type of enriched and enhanced features and services that are provided to the end user. The challenge for next generation PA designers is to provide high efficiency, output power and good linearity across multiple frequency bands, modulation standards and bandwidth. Current industry solution involves parallel PAs dedicated to a single band of operation. As more and more features are added, more and more PAs will be required with increasing cost, area and complexity. As a solution to this problem, one tunable fully integrated class-F power amplifier with reconfigurable output harmonic termination is proposed, designed, fabricated and tested with a commercially available 0.13µm CMOS process technology. By using the coupling between the primary and the secondary winding of an on chip transformer with a variable secondary termination capacitance, the second and third harmonic short and open circuit frequencies are dynamically tuned from 700 MHz to 1200 MHz and achieve high efficiency and output power. To overcome CMOS process low break down voltage, a series voltage combining approach is used for the power device to boost output power, by allowing the power supply to exceed process limits. The fabricated die was packaged and mounted to a printed circuit board for evaluation. Compared to previously publish fully integrated PAs, our design exhibits superior peak power added efficiency, 48.4%, and decent saturated output power and power gain of 24.6 dBm and 16.5 dB respectively with reconfigurability from 700 MHz to 1200 MHz

KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS

Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication. Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges. Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D

RF to Millimeter-wave Linear Power Amplifiers in Nanoscale CMOS SOI Technology

The low manufacturing cost, integration capability with baseband and digital circuits, and high operating frequency of nanoscale CMOS technologies have propelled their applications into RF and microwave systems. Implementing fully-integrated RF to millimeter-wave (mm-wave) CMOS power amplifiers (PAs), nevertheless, remains challenging due to the low breakdown voltages of CMOS transistors and the loss from on-chip matching networks. These limitations have reduced the design space of CMOS power amplifiers to narrow-band, low linearity metrics often with insufficient gain, output power, and efficiency. A new topology for implementing power amplifiers based on stacking of CMOS SOI transistors is proposed. The input RF power is coupled to the transistors using on-chip transformers, while the gate terminal of teach transistor is dynamically biased from the output node. The output voltages of the stacked transistors are added constructively to increase the total output voltage swing and output power. Moreover, the stack configuration increases the optimum load impedance of the PA to values close to 50 ohm, leading to power, efficiency and bandwidth enhancements. Practical design issues such as limitation in the number of stacked transistors, gate oxide breakdown, stability, effect of parasitic capacitances on the performance of the PA and large chip areas have also been addressed. Fully-integrated RF to mm-wave frequency CMOS SOI PAs are successfully implemented and measured using the proposed topology

A review of technologies and design techniques of millimeter-wave power amplifiers

his article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III-V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design

Millimeter-Wave Active Array Antennas Integrating Power Amplifier MMICs through Contactless Interconnects

Next-generation mobile wireless technologies demand higher data capacity than the modern sub-6 GHz technologies can provide. With abundantly available bandwidth, millimeter waves (e.g., Ka/K bands) can offer data rates of around 10 Gbit/s; however, this shift to higher frequency bands also leads to at least 20 dB more free-space path loss. Active integrated antennas have drawn much attention to compensate for this increased power loss with high-power, energy- efficient, highly integrated array transmitters. Traditionally, amplifiers and antennas are designed separately and interconnected with 50 Ohm intermediate impedance matching networks. The design process typically de-emphasizes the correlation between antenna mutual coupling effects and amplifier nonlinearity, rendering high power consumption and poor linearity. This research aims to overcome the technical challenges of millimeter-wave active integrated array antennas on delivering high power (15–25 dBm) and high energy efficiency (≥25%) with above 10% bandwidth. A co-design methodology was proposed to maximize the output power, power efficiency, bandwidth, and linearity with defined optimal interface impedances. Contrary to conventional approaches, this methodology accounts for the correlation between mutual coupling effects and nonlinearity. A metallic cavity-backed bowtie slot antenna, with sufficient degrees of freedom in synthesizing a non 50 Ohm complex-valued optimal impedance, was adopted for high radiation efficiency and enhanced bandwidth. To overcome interconnection’s bandwidth and power loss limitations, an on-chip E-plane probe contactless transition be- tween the antenna and amplifier was proposed. An array of such antennas be- comes connected bowtie slots, allowing for wideband and wide-scan array performance. An infinite array active integrated unit cell approach was introduced for large-scale (aperture area ≈100 λ2) active array designs. The proposed co-design flow is applied in designing a Ka-band wideband, wide scan angle (\ub155\ub0/\ub140\ub0) active array antenna, consisting of the connected bowtie slot radiator fed through the on-chip probe integrated onto the output of a class AB GaAs pHEMT MMIC PA. The infinite array performance of such elements is experimentally verified, presenting a 11.3% bandwidth with a peak 40% power efficiency, 28 dBm EIRP, and 22 dBm saturated power