748 research outputs found

    Dynamic bandwidth allocation in ATM networks

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    Includes bibliographical references.This thesis investigates bandwidth allocation methodologies to transport new emerging bursty traffic types in ATM networks. However, existing ATM traffic management solutions are not readily able to handle the inevitable problem of congestion as result of the bursty traffic from the new emerging services. This research basically addresses bandwidth allocation issues for bursty traffic by proposing and exploring the concept of dynamic bandwidth allocation and comparing it to the traditional static bandwidth allocation schemes

    Performance study of voice over frame relay : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Information Engineering, Massey University, Albany, New Zealand

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    Frame Relay (FR) represents an important paradigm shift in modern telecommunication. This technology is beginning to evolve from data only application to broad spectrum of multimedia users and potential to provide end users with cost effective transport of voice traffic for intra office communication. In this project the recent development in voice communication over Frame relay is investigated. Simulations were carried out using OPNET, a powerful simulation software. Following the simulation model, a practical design of the LAN-to-LAN connectivity experiment was also done in the Net Lab. From the results of the simulation, Performance measures such as delay, jitter, and throughput are reported. It is evident from the results that real-time voice or video across a frame relay network can provide acceptable performance

    Design and performance evaluation of switching architectures for high-speed Internet

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    The motivation for this thesis is the desire to build faster and scalable routers that efficiently handle the exponential traffic growth in the Internet. The Internet forwards information through a mesh of routers and switches, which has to keep up with the increasing demands of traffic. Shared-memory based switches are known to provide the best throughput-delay performance for a given memory size. In this thesis performance of commonly used memory-sharing schemes for the shared memory switches are evaluated under balanced and unbalanced bursty traffic. The scalability of shared-memory switches has been a research issue for quite sometime. One approach is to employ multiple memory modules and use them in parallel to enhance the capacity. The two well-known architectures in this category are (i) shared-multibuffer (SMB) switch architecture invented by Yamanaka et al. of Mitsubishi Electric Corporation, Japan; and (ii) the sliding-window (SW) switch architecture invented by Dr. Kumar of UTPA, Texas, USA. In this thesis, performance of these two architectures are evaluated and compared. Furthermore, in this thesis, the SW switch architecture is extended to enable priority switching to provide differentiated Quality of Service (QoS) for different traffic classes

    Dynamic Time Windows and Generalized Virtual Clocks-Combined Closed-Loop/Open-Loop Mechanisms for Congestion Control of Data Traffic in High Speed Wide Area Networks

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    This paper presents a set of mechanisms for congestion control of data traffic in high speed wide area networks (HSWANs) along with preliminary performance results. The model of the network assumes reservation of resources based on average requirements. The mechanisms address (a) the different network time constants (short term and medium-term), (b) admission control that allows controlled variance of traffic as a function of medium-term congestion, and (c) prioritized scheduling which is based on a new fairness criterion. This latter criterion is perceived as the appropriate fairness measure for HSWANs. Preliminary performance studies show that the queue length statistics at switching nodes (mean, variance and max) are approximately proportional to the end-point \u27time window\u27 size. Further, * when network utilization approaches unity, the time window mechanism can protect the network from buffer overruns and excessive queueing delays, and * when network utilization level is smaller, the time window may be increased to allow a controlled amount of variance that attempts to simultaneously meet the performance goals of the end-user and that of the network. The prioritized scheduling algorithms proposed and studied in this paper are a generalization of the Virtual Clock algorithm [Zhang 1989]. The study here investigates * necessary and sufficient conditions for accomplishing desired fairness, * simulation and (limited analytical results for expected waiting times, * ability to protect against misbehaving users, and * relationship between end-point admission control (Time-Window) and internal scheduling (\u27Pulse\u27 and Virtual Clock) at the switch

    On packet switch design

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